Mcspi usage Summary

1. mcspi controller structure

The SPI bus has a total of four signal lines (CLK clock line, CS chip line selection, Mosi main device output from the device input line, Miso main device input from the device output line, under the control of CLK, the master device and the slave device exchange data in two-way shift registers.

Generally, one or more mcspi (Multi-Channel serial interface) controllers are integrated into the CPU. The internal structure of the controller is 1-1. One controller has one or more channels, and each channel uses an independent register, and each channel corresponds to two DMA requests (read and write), and one intc interrupts the request. Fclk is a function clock, and the clock CLK is provided for Spi through the divider (the value of the divider is set through the Register), iclk is a bus clock, only this clock can be used to read and write the registers in the mcspi controller. The controller can be configured as the master device or slave device, as shown in figure 1-2 and Figure 1-3. The clock signal and chip selection signal are provided internally by the Controller as the master device, and externally provided as the slave device.

When mcspi is the master device, it can be configured as a single-channel operation and multi-channel operation. In single-channel operations, the chip selection signal can be configured as automatic output and software control output. In multi-channel operations, the chip selection signal can only be automatically output.

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Figure 1-1

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Figure 1-2

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Figure 1-3

2. mcspi controller Working Mode

As the mcspi controller of the main device, in order to exchange data with peripherals, the polarity and phase of the serial clock output by the main device can be configured according to the working requirements of peripherals. There are four modes as shown in Figure 2-1 and Figure 2-2.

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Figure 2-1

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Figure 2-2

The clock polarity is used to configure the status when the synchronization clock is idle, which has no significant impact on the transmission protocol, and the clock phase is used to configure the transmission protocol of the SPI bus. If PHA is set to 0, the primary device and slave device prepare data immediately after the selected device is valid (the primary device moves the data to MoSi and the device moves the data to Miso ), output the clock signal after half a clock cycle, that is, sampling the first data along the first clock, as shown in Figure 2-3. If PHA = 1, after the slice is selected as valid, the clock signal starts to be output after the time tlead (the size of tlead can be configured through registers), and the data is output at the same time. After half a clock cycle, the data is ready, that is, the first data is sampled on the second clock edge, as shown in Figure 2-4.

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Figure 2-3

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Figure 2-4

3. Use

In use, you must configure the master device to one of the four modes based on the Mode Supported by the slave device.

Mcspi usage Summary