Measure the test taker's knowledge about anti-interference of single chip microcomputer system software.

In addition to improving the anti-interference ability of hardware systems, software anti-interference is becoming more and more important with its flexible design, saving hardware resources and improving reliability. Taking MCS-51 single-chip microcomputer system as an example, the anti-interference method of computer system software is studied.
1 Research on Anti-interference methods of software
In engineering practice, the main content of the study of anti-interference software is: 1. Eliminate the audible sound of analog input signals (such as digital filtering technology ); 2. How to retrack the program when the program is running in disorder. This article proposes several effective anti-interference methods for the latter.
1.1 instruction redundancy
The CPU command takes the operation code first and then the operand. When the PC encounters an error due to interference, the program will "go off" from the normal track. When it flies to a dubyte command, if the command is always on the operand, the operand will be treated as the operational code by mistake, the program fails. If the "Flying" command reaches three bytes, the error rate is higher.
Insert some single-byte commands manually in key areas, or rewrite valid single-byte commands as command redundancy. Generally, two or more NOP bytes are inserted after the dual-byte command and the three-byte command. In this way, even if the program flies to the operand, the null Operation Command NOP will prevent subsequent commands from being executed as the operand and the program will be automatically put on the right track.
In addition, two NOP can be inserted before commands that play an important role in the system flow direction, such as RET, RETI, LCALL, LJMP, and JC, and the out-of-the-box programs can also be put on the right track, ensure the execution of these important commands.
1.2 interception technology
The so-called interception refers to directing a program to a specified location for error handling. Generally, software traps are used to intercept arbitrary programs. Therefore, it is necessary to design traps rationally, and then arrange traps in appropriate positions.
1.2.1 software trap Design
When a program enters a non-program zone, redundant commands cannot work. Through software traps, attackers can intercept a program, direct it to a specified location, and then handle errors. A software trap is a command used to direct the captured flying program to the reset entry address 0000H. Generally, the following commands are used as software traps in the non-program zone of the EPROM:
NOP
NOP
LJMP 0000 H
The machine code is 0000020000.
1.2.2 trap Arrangement
Generally, enter 0000020000 for the EPROM space that is not used in the program. The last line should be filled with 020000. When the disorderly flying Program falls into this area, the system will automatically enter the track. In the user's program area, you can also enter the idle unit between modules into the trap command. When an interrupt is opened due to interference, you can set a software trap in the corresponding interrupt service program to capture the interrupt of an error in time. If an application system does not use external interrupt 1, the interrupted service program of External Interrupt 1 can be in the following form:
NOP
NOP
RETI
The returned command can be "RETI" or "LJMP ready H ". If the design of the fault diagnosis program and the system self-recovery program is reliable and complete, the "LJMP ready H" command can be used as the return command to directly enter the fault diagnosis program to handle the fault as soon as possible and resume the program operation.
Considering the size of the program memory, the software traps can be effectively intercepted if there are 2-3 1 K space.
1.3 software "dog" technology
If an out-of-control program enters an "endless loop", the "Watchdog" Technology is usually used to remove the program from the "endless loop ". By constantly checking the program running time, if the program running time exceeds the maximum running time, the system is considered to be in an "endless loop" and errors must be handled.
The "Watchdog" technology can be implemented by hardware or software. In industrial applications, serious interference sometimes breaks down the interrupt control word and closes the interrupt. The system cannot "Feed the dog" regularly, and the hardware watchdog circuit fails. The software guard can effectively solve such problems.
In practical application, the circular interrupt monitoring system is used. The timer T0 is used to monitor the timer T1, the timer T1 is used to monitor the main program, and the main program monitors the timer T0. The software "Watchdog" using this ring structure has good anti-interference performance and greatly improves the system reliability. For the need to often use T1 timer serial communication of the measurement and control system, the timer T1 can not be interrupted, can be changed by the serial port interrupt monitoring (if the use of MCS-52 series microcontroller, t2 ). The software "Watchdog" monitoring principle is: in the main program, T0 interrupt service program, T1 interrupt service program, each set a line of observation variables, such as MWatch, T0Watch, T1Watch, every cycle of the main program, MWatch plus 1, T0, T1 interrupt service program execution once, T0Watch, T1Watch plus 1. In the T0 interrupt service program, check the changes of T1Watch to determine whether T1 runs normally. In the T1 interrupt service program, check the changes of MWatch to determine whether the main program runs normally, in the main program, check the T0Watch changes to determine whether T0 works normally. If an abnormal observed variable change is detected, for example, 1 should be added without 1, the error handling program will be switched to for troubleshooting. Of course, the maximum cycle of the main program, Timer T0 and T1 timing cycle should be fully and reasonably considered. We will not repeat the length.
2 System Fault Handling and self-Recovery Program Design
If the single-chip microcomputer system is reset due to interference or power loss, the reset is abnormal. fault diagnosis should be performed and the status before the reset can be automatically restored.
2.1 Abnormal Reset Identification
The execution of the program always starts from running H, and there are four possibilities for executing the program starting from running H: 1. Resetting the system upon power-on; 2. Resetting the software fault; 3. Reset hardware when the watchdog times out and the dog is not fed; 4. Power loss when the task is being executed, and power reset. In four cases, except for the first case, the reset operation is abnormal and needs to be identified.
2.1.1 hardware reset and software reset Identification
Here, hardware reset refers to boot reset and watchdog reset. hardware reset affects registers, such as PC = 0000 H, SP = 07 H, PSW = 00H after the reset. Software resetting has no effect on SP and SPW. Therefore, for a microcomputer measurement and control system, when the program runs normally, set the SP address to be greater than 07 H, or set the 5th-bit user flag of PSW to 1 during normal system operation. When the system is reset, you only need to check the PSW.5 flag or SP value to determine whether the hardware is reset. Figure 1 shows the program flow chart that uses ps00005 as the power-on flag to identify hard and software reset.

Figure 1 hardware and software reset recognition Flowchart
In addition, the on-chip RAM status is random when the hardware is reset, while the on-chip RAM can be kept in the pre-Reset status, therefore, you can select one or two units in the chip as the power-on sign. Set the power-on sign to 40 H, and the power-on sign to 78 H. If the content of the 40 H unit after the system is reset is not equal to 78 H, it is considered as a hardware reset; otherwise, it is considered as a software reset, turning to error handling. If two units are used as the power-on mark, the reliability of this method is higher.
2.1.2 identification of boot reset and watchdog fault Reset
Boot reset and watchdog fault reset are both hardware reset, so to correctly identify them, we generally need to use non-volatile RAM or EEROM. When the system is running normally, set an observation unit that can be protected by power loss. When the system is running normally, keep the observation unit normal (set to AAH) in the interrupt service program of timed dog feeding, and reset the unit in the main process, because the observation unit is protected by power loss, you can determine whether to reset the watchdog by checking whether the unit is normal at startup.
2.1.3 identification of normal and abnormal boot resetting
It is particularly important for the process control system to identify boot reset and normal boot reset caused by unexpected circumstances such as system power loss in the measurement and control system. For example, a time-based measurement and control system takes one hour to complete a measurement and control task. When the measurement and control has been performed for 50 minutes, the system voltage exception causes the reset. At this time, if the system resets and starts the measurement and control from the beginning, it will cause unnecessary time consumption. Therefore, a monitoring unit can be used to monitor the running status and System Time of the current system, and the control process can be divided into several steps or several time periods, the value of the monitoring unit is set to the value of shutdown after each step or period of operation. Different tasks or tasks have different values for different stages, if the system is performing a measurement and control task or holding a period of time, the monitoring unit is set to an abnormal shutdown value. After the system is reset, you can determine the original running status of the system based on the unit and jump to the error handling program to restore the original running status of the system.
2.2 Program Design for auto-recovery after Abnormal Reset
Some Process Control Systems with strict sequence requirements and abnormal system resetting are not required. Generally, it is required to resume operation from the out-of-control module or task. Therefore, the measurement and control system must back up important data units and parameters, such as the system running status, system process value, current input and output value, current clock value, and observation unit value, the data must be backed up on a regular basis and immediately if any modification is made.
When the abnormal reset of the system has been identified, necessary system data should be restored first, such as the initialization of the display module and the initialization of the chip extension. Then, the system status and operating parameters of the measurement and control system are restored, including the restoration of the display interface. Then, the tasks, parameters, and running time before resetting are restored, and then the system is running.
It should be noted that it is necessary to back up important data of the system and check the reliability of the data to ensure the reliability of the recovered data.
Secondly, for multi-task and multi-process measurement and control systems, the order of data recovery needs to be taken into account. The data recovery process flow chart 2 in my actual application shows.
Figure 2 flowchart of the system self-recovery program
In the figure, basic system data recovery means that the backup data is taken out to overwrite the current system data. System initialization refers to the initialization of the chip, display, and input/output modes. Note that initialization of input/output should not lead to incorrect operations. Task initialization before resetting refers to the execution status and running time of the task.
3 conclusion
This article does not discuss other common anti-interference methods, such as digital filtering, RAM data protection, and error correction. In engineering practice, there are usually several anti-interference methods used to complement each other and improve each other in order to achieve better anti-interference effect. Basically, hardware anti-interference is active, while software anti-interference is passive. It is feasible to carefully analyze the interference sources, combine hardware and software anti-interference, improve the system monitoring program, and design a stable and reliable single-chip microcomputer system.