Memory barrier Parallel programming

Concurrent programming

Memory barrier (RAM fence)

CPU Level
1.CPU has a number of pipeline, executing code, will execute code in parallel, so the CPU needs to assign the program instructions to each pipeline to execute separately, this is disorderly execution;
2.CPU has read Buffer/write buffer these 2 read-write cache, these 2 parts used to cache CPU memory read and write operations, not real-time synchronization to the CPU cache (L1/L2/L3), this will cause the update of a piece of memory, the other CPU is not aware;
Read the time, priority to read buffer to find data, found, the use of this data, if the memory of this data has been updated, then read the data is outdated data, this read, write not timely problems, unity is called data inconsistency.

Above 2 questions, collectively referred to as memory barrier

Note: As long as the data is in the CPU cache (L1/L2/L3), the other CPUs can sense that when writing the data, it is guaranteed to write to the cache.

For the above 2 issues, the CPU provides memory barrier related instructions to solve these 2 problems
Let's use X86 CPU to explain

Sfence
This is the "write fence" command, the specific semantics are:
1. Flush the write buffer and swipe the cache write to the CPU cache to ensure that the other CPUs can perceive
2. Instruction disorderly order guarantee.
Sfence all the write instructions in front of this instruction and all subsequent write instructions are executed sequentially
(The order here is the order of the blocks, such as the previous 1 2 33 write instructions, followed by 4 5 63 write instructions,
Guarantee 1 2 3 is certainly more than 4 5 6 in any one of the earlier, 4 5 6 of these 3 instructions, certainly more than any 1 2 3 in the execution of the night, as for 1 2 3 The order of the three instructions, as determined by the CPU)
Lfence
This is the "read fence" command, the specific semantics are:
1. Clear read buffer, clear the appropriate registers, and ensure subsequent reads to the cache to read the data in order to sense the other CPU write action
2. Instruction disorderly order guarantee.
Lfence all read instructions in front of this instruction and all subsequent read instructions are executed sequentially
(The order here is the order of the blocks, such as the previous 1 2 33 read instructions, followed by 4 5 63 Read instructions,
Guarantee 1 2 3 is certainly more than 4 5 6 in any one of the earlier, 4 5 6 of these 3 instructions, certainly more than any 1 2 3 in the execution of the night, as for 1 2 3 The order of the three instructions, as determined by the CPU)
Mfence
This is the "read/write Fence" command, with the following specific semantics:
1. Clear the Read buffer, clear the appropriate registers, flush the write buffer to ensure that subsequent reads to the cache to read the data in order to sense the other CPU write action, while ensuring that the written data can be sensed by other CPUs
2. Instruction disorderly order guarantee.
Mfence all read/write instructions in front of this instruction and all subsequent read/write instructions are executed sequentially
(The order here is the order of the blocks, such as the previous 1 2 33 read/write instructions, followed by 4 5 63 read/write instructions,
Guarantee 1 2 3 is certainly more than 4 5 6 in any one of the earlier, 4 5 6 of these 3 instructions, certainly more than any 1 2 3 in the execution of the night, as for 1 2 3 The order of the three instructions, as determined by the CPU)


Compiler Level

is to compile parameters, partially limit the compiler's optimization, to ensure the sequence of compiled instructions, there is the instruction queue to insert the corresponding CPU memory barrier related instructions, such as CPU execution instructions, control CPU memory barrier behavior

Programmatic impact

Volatile this variable, there is memory barrier semantics, which is guaranteed by the compiler, when accessing the volatile variable, the compiler before and after access to automatically insert the relevant memory barrier instructions,
Java compilation inserts lfence before accessing the volatile variable, inserting sfence after writing the volatile variable, ensuring memory visibility

Then there is compiler-related compiler macros (c + +)

Memory barrier Parallel programming