Multi2sim and dramsim links

Introduction:

A common tool for system structure experiments is the simulator. Multi2sim is a precise multi-core clock simulator that supports a variable storage hierarchy. Currently, network connections only support bus and P2P, but the simulation of memory simply returns a cycle latency, there are great limits on the study of memory controllers. Dramsim is a memory clock precision simulator. Therefore, the work in this article is to connect multi2sim with dramsim for more powerful functions.

Source code:

1. multi2sim: A CPU-GPU model for Heterogeneous Computing

Http://download.csdn.net/detail/koala002/3857207 (csdn)

2. dramsim: dramsim2 is a cycle accurate model of a DRAM Memory Controller

Http://download.csdn.net/detail/koala002/3857463 (csdn)

Steps:

1. Solve the connection problem between C ++ and C Programs

Multi2sim and dramsim interface files: Because the automake tool family uses the CC variable compiler for *. c suffix files, and the *. cpp suffix uses the cxx variable compiler, the suffix is changed to. cpp.

Libcachesystem/cachesystem. cpp

First, include the header file at the beginning of the file, define the memory read/write processing function, and define a global memory instance pointer

#ifdef MACRO_DRAM_SIM#include "../libdram/MemorySystem.h"class some_object{public: void read_complete(unsigned, uint64_t, uint64_t);void write_complete(unsigned, uint64_t, uint64_t);int add_one_and_run();};/* callback functors */void some_object::read_complete(unsigned id, uint64_t address, uint64_t clock_cycle){//esim_schedule_event(EV_MOESI_FIND_AND_LOCK_FINISH, stack, ccache->lat);//printf("[Callback] read complete: %d 0x%lx cycle=%lu\n", id, address, clock_cycle);}void some_object::write_complete(unsigned id, uint64_t address, uint64_t clock_cycle){//esim_schedule_event(EV_MOESI_FIND_AND_LOCK_FINISH, stack, ccache->lat);//printf("[Callback] write complete: %d 0x%lx cycle=%lu\n", id, address, clock_cycle);}/* FIXME: this may be broken, currently */void power_callback(double a, double b, double c, double d){printf("power callback: %0.3f, %0.3f, %0.3f, %0.3f\n",a,b,c,d);}/* init one dramsim instance */class MemorySystem* g_dramsim_memory;#endif

Second, cache_system_init is a storage level creation function. It applies for a memory instance and registers a read/write function.

#ifdef MACRO_DRAM_SIM    /* new one instance */    g_dramsim_memory= new MemorySystem(0, "ini/DDR2_micron_16M_8b_x8_sg3E.ini",\        "system.ini", "/home/jyq/multi2sim-3.1.1/src/libdram", "resultsfilename", 1024*500);    /* create and register our callback functions */Callback_t *read_cb = new Callback<some_object, void, unsigned, uint64_t, uint64_t>(new some_object, &some_object::read_complete);Callback_t *write_cb = new Callback<some_object, void, unsigned, uint64_t, uint64_t>(new some_object, &some_object::write_complete);    g_dramsim_memory->RegisterCallbacks(read_cb, write_cb, power_callback);#endif

Libcachesystem/MOESI. cpp: consistent protocol operation, read/write operation

First, the header file contains, and note that extern "C" is added to both ends of the Code to ensure compatibility with the original code.

#ifdef MACRO_DRAM_SIM#include "../libdram/MemorySystem.h"extern MemorySystem* g_dramsim_memory;#endifextern "C"{#include "cachesystem.h"

Second, the moesi_find_and_lock function is a block function, which is required for read/write operations.

If no lonet is found, it is the last-level cache. It is like inserting transaction into the memory.

#ifdef MACRO_DRAM_SIM        /* create a transaction and add it */if(!ccache->lonet){Transaction tr = Transaction(stack->read?DATA_READ:DATA_WRITE,stack->addr, stack);g_dramsim_memory->addTransaction(tr);}#endif

In the original code memory simulation, only 200 cycles is returned. Therefore, if a non-memory read operation is detected, latency is added directly. Otherwise, after the memory operation is returned, the read/write completes the registration function processing.

#ifdef MACRO_DRAM_SIM/* Access latency */if(ccache->lonet ){esim_schedule_event(EV_MOESI_FIND_AND_LOCK_FINISH, stack, ccache->lat);}#elseesim_schedule_event(EV_MOESI_FIND_AND_LOCK_FINISH, stack, ccache->lat);#endif

Ibcpuarch/cpuarch. cpp

Void cpu_run (): Implements precise clock simulation. The sub-function cpu_stages () is used to retrieve, decode, execute, submit, and write back the clock in each cycle, therefore, add the memory update operation later. Pay attention to the frequency multiples between the processor and the memory.

#ifdef MACRO_DRAM_SIM

        /* Dramsim stage*/        extern class MemorySystem* g_dramsim_memory;        g_dramsim_memory->update();#endif

2. To minimize code changes, compile dramsim into a dynamic link library and link it to the multi2sim code at the link.

3. During code merging, the void * pointer is allowed to be assigned to other types of pointers in the C standard, but the C ++ annotation is not allowed, therefore, when you use g ++ to compile some source files, you must convert the type at these assignment locations.

4. For more information about makefile rewriting, see automake and configure.

5. This article is just a general change to the framework, and the implementation or expansion of detailed functions need to be further rewritten.