Net2272.c code analysis -- initprocessorspecificconfiguration

The function is defined as follows:

Section ("l1_code") int initprocessorspecificconfiguration (adi_net2272_device * pdev) <br/>{< br/> unsigned short usvalue; <br/> volatile unsigned int V; </P> <p> # If defined (_ adspbf533 __) <br/>/* configure interrupt flag as level sensitive input from net2272 */<br/> usvalue = * pfio_inen; <br/> * pfio_inen = usvalue | pdev-> pf_int; <br/> usvalue = * pfio_dir; <br/> * pfio_dir = usvalue &~ (Pdev-> pf_int); <br/> usvalue = * pfio_edge; <br/> * pfio_edge = usvalue &~ (Pdev-> pf_int); <br/> usvalue = * pfio_maska_d; <br/> * pfio_maska_d = usvalue | pdev-> pf_int; <br/> usvalue = * pfio_polar; <br/> * pfio_polar = usvalue | pdev-> pf_int; </P> <p>/* configure the set and clear flags as outputs and perform set or clear */<br/> usvalue = * pfio_dir; <br/> * pfio_dir = usvalue | pdev-> pf_set | pdev-> pf_clear; <br/> * pfio_flag_c = pdev-> pf_clear; <br/> * pfio_flag_s = pdev-> pf_set; </P> <P> # Elif defined (_ adspbf537 _) <br/>/* configure interrupt flag as level sensitive input from net2272 */<br/> usvalue = * pportfio_inen; <br/> * pportfio_inen = usvalue | pdev-> pf_int; <br/> usvalue = * pportfio_dir; <br/> * pportfio_dir = usvalue &~ (Pdev-> pf_int); <br/> usvalue = * pportfio_edge; <br/> * pportfio_edge = usvalue &~ (Pdev-> pf_int); <br/> usvalue = * pportfio_maska; <br/> * pportfio_maska = usvalue | pdev-> pf_int; <br/> usvalue = * pportfio_polar; <br/> * pportfio_polar = usvalue | pdev-> pf_int; </P> <p>/* configure the set and clear flags as outputs and perform set or clear */<br/> usvalue = * pportfio_dir; <br/> * pportfio_dir = usvalue | pdev-> pf_set | pdev-> pf_clear; <br/> * pportfio_clear = pdev-> pf_clear; <br/> * pportfio _ Set = pdev-> pf_set; </P> <p> # Elif defined (_ adspbf561 __) <br/>/* set the input interrupt mark from net2272 to Level Trigger */<br/>/* configure interrupt flag as level sensitive input from net2272 */<br/> usvalue = * pfio0_inen; /* read the interrupt enable register value */<br/> * pfio0_inen = usvalue | pdev-> pf_int; /* configure the fio0_inen register */</P> <p> usvalue = * pfio0_dir; <br/> * pfio0_dir = usvalue &~ (Pdev-> pf_int); </P> <p> usvalue = * pfio0_edge; <br/> * pfio0_edge = usvalue &~ (Pdev-> pf_int); </P> <p> usvalue = * pfio0_maska_d; <br/> * pfio0_maska_d = usvalue | pdev-> pf_int; </P> <p> usvalue = * pfio0_polar; <br/> * pfio0_polar = usvalue | pdev-> pf_int; </P> <p>/* configure the set and clear flags as outputs and perform set or clear */<br/> usvalue = * pfio0_dir; <br/> * pfio0_dir = usvalue | pdev-> pf_set | pdev-> pf_clear; <br/> * pfio0_flag_c = pdev-> pf_clear; <br/> * pfio0_flag_s = pdev-> pf_set; </P> <p> # else <br/> # error *** processor not supported *** <br/> # endif </P> <p>/* Delay for a bit */<br/> for (V = 0; v <0 xfffff; V ++) <br/>; </P> <p> return 0; <br/>}

The data type of the function parameter is adi_net2272_device. Its definition is as follows:

/* Kernel device structure of net2272, is an excuse for the host and net2272 drivers */<br/>/* net2272 core device structure */<br/> typedef struct net2272devicedata <br/> {<br/> adi_dev_device_handle devicehandle; /* Device handle */<br/> adi_dma_manager_handle dmahandle;/* DMA control handle */<br/> adi_dcb_handle dcbhandle;/* Data Control Block (DCB) handle */<br/> adi_dcb_callback_fn dmcallback;/* callback function */<br/> adi_dev_direction direction;/* Device direction */<br/> void * pcriticalregionarg; /* bool started parameter pointer */<br/> bool started;/* Start flag */<br/> device_state state; /* device status */<br/> physical_endpoint_object physicalendpointobjects [num_physical_endpoints];/* Physical endpoint object */<br/> int numphysicalendpoints; /* Number of physical point points */<br/> adi_dma_stream_id dmastreamid;/* ID of the DMA stream */<br/> void * dmachannelhandle; /* DMA channel handle */<br/> adi_int_peripheral_id peripheralid;/* peripheral device ID *, <br/> u32 peripheralivg; /* peripheral device interruption vector table */<br/> int pf_reset;/* PF (Programmable flag) angle reset */<br/> int pf_int; /* pf angle interruption */<br/> int pf_clear;/* pf angle clearing */<br/> int pf_set; /* pf angle setting */<br/> int DeviceID;/* device ID */<br/> device_object * pdeviceobj; /* device object pointer */<br/> net2272_stats stats;/* net2272 status */<br/> bool cache; /* cache */<br/> void * configmemoryarea;/* configure the memory area pointer */<br/> int configmemorysize; /* configure the memory size */<br/> int bufferprefix;/* buffer prefix */<br/> adi_usb_device_speed; /* USB device speed */<br/>} adi_net2272_device;

Because I use adspbf561, I only analyze the adspbf561. Before analysis, it is necessary to introduce the fion_xxx register.

 

1: Flag input enable register (fion_inen)

The flag input enable register is used to enable the input buffers on any flag pin that is being used as an input. leaving the input buffer disabled eliminates the need for pullups and pulldowns when a particle pfx pin is not used in the system. by default, the input buffers are disabled.

 

2: Flag direction register (fion_dir)

The flag direction register is a read-write register. each bit position corresponds to a pfx pin. A logic 1 configures a pfx pin as an output, driving the State contained in the fion_flag_d register. A logic 0 configures a pfx pin as an input. the reset value of this register is 0x0000, making all pf pins inputs upon reset.

Note: note that when using the pfx pin as an input, the corresponding bit shoshould also be set in the flag input enable register.

 

3: Flag interrupt sensiti1_register (fion_edge)

The flag interrupt sensiti1_register is used to configure each of the flags as either a level-sensitive or an edge-sensitive source. when using a edge-sensitive mode, an edge-detection circuit is used to prevent a situation where a short event is missed because of the system clock rate. this register has no effect on pfx pins that are defined as outputs.

The contents of this register are cleared at reset. Defaulting to level sensiti.pdf.

 

4: Flag mask interrupt Data Register (fion_maska_d)

The flag mask interrupt registers are implemented as complementary pairs of write-1-to-set, write-1-to-clear, and write-1-to-Toggle registers. this implementation provides the ability to enable or disable a pfx pin to act as an interrupt without requiring read-Modify-write accesses-or to directly specify the mask value with the data register.

Both flag interrupt a and flag interrupt B are supported by a set of four dedicated registers:

• Flag mask interrupt Data Register
• Flag mask interrupt set register
• Flag mask interrupt clear register
• Flag interrupt toggle register

Each pfx pin is represented by a bit in each of the eight registers. table 14-5 shows the effect of writing 1 to a bit in a mask set, mask clear, or mask toggle register.

Table 14-5. Effect of writing 1 to a bit

Register	Effect of writing 1 to a bit in the register
Mask set	Enables interrupt generation for that pfx pin
Mask clear	Disables interrupt generation for that pfx pin
Mask toggle	Changes the state of Interrupt generation capability
Mask data	Enables interrupt generation for that pfx pin

 

4: Flag polarity register (fion_polar)

The flag polarity register is used to configure the polarity of the Flag Input Source. To select active high or rising edge, set the bits in this register to 0.

To select active low or falling edge, set the bits in this register to 1.

This register has no effect on pfx pins that are defined as outputs. The contents of this register are cleared at reset, defaulting to active high polarity.

 

Because you want to set the input interrupt of net2272 to a Level Trigger, read the input enable register value first.

Usvalue = * pfio0_inen;

 

Then, modify fio0_inen according to the property pf_int value of the device.

* Pfio0_inen = usvalue | pdev-> pf_int;

 

Read the PF direction register value

Usvalue = * pfio0_dir;

 

Set the Enable bit corresponding to the interrupt enable register to the input angle.

* Pfio0_edge = usvalue &~ (Pdev-> pf_int );

 

Read data mask bit

Usvalue = * pfio0_maska_d

Enable corresponding PIN interruption

* Pfio0_maska_d = usvalue | pdev-> pf_int;

 

Set the input pin to a high-level trigger and use it with fion_edge.

Usvalue = * pfio0_polar;

* Pfio0_polar = usvalue | pdev-> pf_int;

 

Because adsp is the receiver and input from net2272, adsp must control net2272 through fion_flag_c & fion_flag_s.

Usvalue = * pfio0_dir;
* Pfio0_dir = usvalue | pdev-> pf_set | pdev-> pf_clear;/* set to output */
* Pfio0_flag_c = pdev-> pf_clear;
* Pfio0_flag_s = pdev-> pf_set;

The preceding statements configure the set and clear tags as output to execute the set or clear

 

According to the above analysis, this function is mainly used to configure the corresponding pf pins so that net2272 and adspbf561 can communicate with each other through the corresponding pins.