NOR Flash Erase and Principle Analysis (ii)

Nor Flash is in the data read state (Reading Array data) after power-on. This state can be read normally. This is the same as reading Sdram/sram/rom. (if not the same, how to read the boot code from the Norflash after the chip is power-on .) ~)

Generally before the operation of Flash to read the chip information such as the device ID number. The main purpose of this is to determine whether the program you write supports the device. Nor Flash supports 2 ways to get ID numbers. One is that the method used by the programmer requires a high voltage (11.5v-12.5v). Another method is the so-called In-system method, which is done through the norflash Command register in the system. Only the In-system method is described in this article. You need to switch to automatic selection (autoselect command), which is done by sending a command. See the command type. Note:

After entering the auto-select (autoselect command) mode, a reset command is sent to return to the data read state (Reading Array data).

It is generally necessary to erase data after completion of the information acquisition. the Norflash supports sector wipe (Sector Erase) In addition to the whole piece erase (Chip Erase). each of these 2 modes has a corresponding command sequence. After the erase command is complete, it is automatically returned to the data read (Reading Array data) state. The state of the program can be queried before returning.

When you finish erasing, you need to write to the chip, which is programming. This requires entering the programming state. The data read (Reading Array data) state is automatically returned when the programming command is completed. The state of the program can be queried before returning. Note: Be sure to erase before programming. Because programming can only rewrite ' 1 ' to ' 0 ', erase the data by erasing it all as '1 '.

The above is the main operation of other operations and write protection, etc., please refer to the chip data sheet.

Figure 1-1 Commands and Patterns

(2) Nor Flash Hardware connection

Figure 2-1 Nor Flash Pin

Figure 2-2 TQ2440 actual connection in

Some of the areas to note:

1. pin byte#: when it is high, the data output is 16bit mode ( At this point the address line is a19:a0). Low Level is 8bit Mode . ( At this point the address line is a19:a1) the Pin47 plus VCC is selected 16bit mode valid address line is a19:a0.

2.for16bitmode to16bitAlignment Sos3c2440aof theLADDR1to be withA0Connection.It's important to note at this pointNorflashOn- chip address0x555correspondings3c2440athe address isbaseaddr+0x555*2;whichbaseaddrwith theNorflashthe address of the map. GeneralNorflashplaced inBank0.sobaseaddr=0,but openMMUafterbaseaddr=Address0the new address to which the map is mapped. 0x555*2the reason isLADDR1with theA0connection. Also0x555indicates that the section on the chip0x555aWord (16bit).

3. The pin is a ryby# output pin. Used to output ready and Busy signals. Actual time can not be answered. Use the command query norflash state instead .

(3) Nor Flash mode programming

1. read ID

Indicates that the Read ID has 4 instruction cycles , the Money 3 is the write cycle , the last one is the reading period ;

#define Flash_base 0x00000000//flash received on Bank0

#define CMD_ADDR0 * (Volatile U16 *) (0x555*2+flash_base)

#define CMD_ADDR1 * (Volatile U16 *) (0x2aa*2+flash_base)

#define CMD_ADDR2 * (Volatile U16 *) (0xaaa*2+flash_base)

/*** Read am29lv800d ID ***/

U32 get_am29lv800d_id (void)

{

U32 i= "0";

Cmd_addr0 = 0xaa; CMD_ADDR1 = 0x55; Cmd_addr0 = 0x90;

i = (* (* (U16 *) (0*2+flash_base)) <<16;//manufacturer ID =

Cmd_addr0 = 0XAA; CMD_ADDR1 = 0x55; Cmd_addr0 = 0x90;

I |= * (U16 *) (1*2+flash_base);//device ID = 2249

return i;

}

2. Sector erase (Sector Erase)

each period of a Sector erase command sequence is a write cycle.

void Am29lv800d_sectorerase (U32 SA)

{

Cmd_addr0 = 0xAA; CMD_ADDR1 = 0x55; Cmd_addr0 = 0x80;

Cmd_addr0 = 0xAA; CMD_ADDR1 = 0x55;//word mode command sequence

* (Volatile U16 *) (SA) = 0x30;

WAITFOR_ENDOFPRG ();//Status query

}

3. Programming (Program )

Programming each period of a command sequence is a write cycle.

int Am29lv800d_wordprog (U32 pa,u16 PD)

{

Cmd_addr0 = 0xAA; CMD_ADDR1 = 0x55; Cmd_addr0 = 0xA0;

* ((Volatile U16 *) (PA)) = pd;// Word mode, above 4 command cycles

Return (WAITFOR_ENDOFPRG ());//Status query

}

4. Write action status (write operation status)

Norflash provides several data bits to determine the state of a write operation, namely : DQ2, DQ3, DQ5, Dq6,dq7, and ry/by#. As shown in. Each of the DQ7, ry/by# pins , and DQ6 provides a way to determine whether a program or erase operation has completed or is in progress. Only one of these needs to be used in real programming.

DQ7:data# Polling bit,DQ7 state changes during programming .

The DQ7 of the data that is read from the address being programmed during programming is the complement of the data to be written. For example, the data written is 0x0000, and the input DQ7 is '0 ', the data read in the programming is '1 ', and when the programming is completed, the data is read back to the input data as ' 0 '.

The DQ7 output is ' 0 ' during the erase process, and the output is ' 1 ' When the erase is complete; note that the address to be read must be an address within the erase range.

ry/by # : high indicates ' ready ', low level means ' busy '.

DQ6 : Rotary bit 1 ( Toggle Bit 1 ).

During programming and erasing, reading any address will result in the rotation of the DQ6 (0,1 transforms each other ). When the operation is complete, DQ6 stops the conversion.

DQ2: rotary bit 2(Toggle bit 2). when a sector is selected for Erasure, the read valid address (the address is within the erased sector) causes the DQ2 to rotate.

Note : DQ2 can only determine if a particular sector is selected for Erasure. But you can't tell whether this is going to be erased or is in the erase pause state. In contrast,DQ6 can differentiate whether Norflash is in the erase or erase state , but cannot distinguish which is quickly selected for erasing. These 2 bits are therefore required to determine sector and pattern state information.

DQ5: The timeout bit (exceeded Timing Limits), when the program or erase operation exceeds a specific internal pulse count is dq5=1, which indicates that the operation failed. When programmed to change ' 0 ' to ' 1 ' will result in Dq5=1, because only erase wipe can change ' 0 ' to ' 1 '. A reset command (see figure 1-1) is required to return to the read data state when an error occurs.

DQ3: (Sector erase timer ) Sector Erase timer, only works when the sector erases instructions. When the erase instruction really begins to work Dq3=1, the command entered (except for the Erase Pause command) is ignored. dq3=0, it is possible to add additional sectors for multi-sector erase.

Above said these states for, actually only need to use a few on the line, relatively simple is to choose DQ5,DQ6/DQ2. The following example.

Detection of/****** am29lv800d ******/

int Waitfor_endofprg (void)

{

Volatile U16 Flashstatus,old;

old=* (Volatile U16 *) 0x0);//Read First state

while (1)

{

flashstatus=* (Volatile U16 *) 0x0);//re-read status

if ((old&0x40) = = (flashstatus&0x40)) break;//compare DQ6. Same description device is ready

if (flashstatus&0x20)//Judge DQ5, '1 ' then timeout

{

old=* (Volatile U16 *) 0x0);

flashstatus=* (Volatile U16 *) 0x0);//Read comparison once. Because it might just be fun before the timeout.

into operation.

if ((old&0x40) = = (flashstatus&0x40))

return 1;

else return 0;

}

Old=flashstatus;

}

return 1;

}

Norflash Erase & Programming Issues
Recent programming in Test Norflash:
Each time the sector is erased, the operation can be successful with the method of delay. But the method of toggle bit detection fails every time. Best of all, I also refer to the "32-bit embedded system hardware design and debugging" (Zhanglong) a book, in the Internet also search a lot of reference code, but always not ... ^_^
Experienced friends in this area, please give a point of view, if you can provide the actual combat test toggle or polling testing procedures, will not be very grateful!!!

NOR Flash Erase and Principle Analysis (ii)