Notes (1) -- Overview

The HDL language is a description of hardware. This feature gives it the concept of "concurrency". It is very exciting to consider it from the perspective of language alone. The basic unit of description is the module. Although the hardware makes him more limited than C, the combination of modules with "concurrency" also gives him the flexibility to be underestimated. Port type Input is of the wire type by default (it does not seem to be declared as Reg type); when output is assigned in always or initial, Reg is used by default; otherwise, wire is used; inout is generally set to the Tri type (it indicates there are multiple driver sources, if there is no driver, it is three States) Data Type 0. constant: parameter name 1 = expression, parameter name 2 = expression ,..., parameter Name n = expression; 1. wire and Tri wire networks are used to model the physical connections of structured devices. (For example, the pin of a device, the internal device, and the door output). Because the network type represents a physical connection, it does not store the logical value. The device must be driven. Generally, assign is used to assign values. The default value of a wire signal is Z. When no data type is defined for a signal, the default value is wire. TRI is mainly used to define a three-state network. 2. Register Type Reg is the most common register type, which is usually used to describe the storage unit. Such as D Trigger and Rom. Reg variables are not necessarily storage units. Reg-type variables must be described in the always statement. II. Operator 1. arithmetic Operators: +,-, *,/, % 2. relational operators: ">", "<", "> =", "<=", "=" (equal logic ),"! = "(Logical) the result of the relational operator is 1 or 0. If one of the operands is X or Z, the result is X. If the operand length is different, the shorter operand must be filled with 0 on the left. Note: "=" and "! = "When the operands are compared, the undefined values of some bits X and high-impedance Z are also compared. The two operands must be completely consistent and the result is 1; otherwise, the result is 0. 3. logical operators & |! 4. bitwise logical operators (~, &, |, ^, "^ ~ "(Distinct or not) 5. Conditional OPERATOR: expr1? Expr2: expr3 6. bitwise concatenation operator: {expr1, expr2,..., exprn} combines small expressions into large expressions. Eg: wire [] California; assign California [] = {California [0], California [1], California [2], California [3]}; // The Reverse Order of the low position is assigned to the high position assign priority = {priority [], priority []}; // the exchange between the high position and the low position. Note: non-fixed-length constants cannot be connected. Example: {condition, 5} 7. Shift Operator (<and>) 8. Condition Statement: If statement. Case statement: the default item of case must be written to prevent latches. 9. Reduce OPERATOR: &, | ,~ Eg. reg [3: 0] B; Reg C; C = & B; // equivalent to C = B [0] & B [1] & B [2] & B [3]; 10. priority:

! ,~ Advanced Level *,/, % +,-<, >><, <=,>, >== ,! =, = ,! ==& ^, ^ ~ | & |? :

BLOCK statement: 1. Ordered block: The in-block statement completes begin order... End 2. Parallel Block: fork... Join 3. Modeling 1. Structure Modeling: Call module. In structural modeling, the description statement is mainly an instantiation statement, including examples of built-in gate (and) in the Tilde language (HDL) or gate (XOR. Call other devices. The devices here include some macro units provided by FPGA manufacturers and the existing design of the designers. A. Handling of floating ports and ports of different lengths during module instantiation (that is, calling): When a floating port is input, it serves as a high-impedance Z. When the floating port is output, this pin is discarded. When the port length is different from that of the local port expression, the port is matched by the right alignment or truncation of the unsigned number. 2. Data Stream modeling. Continuous value assignment statement: Assign net_type = expression; continuous value assignment statement is used for modeling the combination logic. The data type on the left is wire. Consecutive value assignment statements are parallel statements, so they are irrelevant to Location Order. = Used for blocking value assignment. Use blocking value assignment to assign values in the combination logic (for example, in the assign Statement. 3. Behavior Modeling: design modeling is achieved by describing the design behavior. It is generally designed to be behavior modeling by using the process value assignment statement (initial and always statements. A. The sequence statement block combines two or more statements into an idiom structure equivalent to a statement. For example, the sequential statement block (begin... End ). The statements in the statement block are executed in the given order. B. Value assignment statement. Two Value assignment statements, initial and always, are provided in each of the two procedures. These two statements are executed in parallel. These two statements are usually used with the statement block (begin... End. Initial statement: the initial statement is executed only once, that is, it starts when the design is started to simulate the execution (0 moment ). Always statement: the always statement is executed repeatedly. The execution mechanism is implemented by an event driver that becomes a sensitive variable table. The always statement can be used to model the combination logic or time series logic. Always @ (posedge CLK or posedge RST) the entire always statement is executed when the sensitive variable changes. Otherwise, it is not executed. The sensitive variable in [email protected] (*) is *, which means that the sensitive variable is automatically added by the synthesizer according to the input variable in always. Note: for the always statement of the combination logic, sensitive variables must be fully written. Block assignment is used to assign values to the logical devices of the combination. The assign value statement of the logical devices of the time series uses non-blocking assignment. "<="

 

Notes (1) -- Overview