Oc8051 internal logic analysis (1)

When using data streams for logical analysis within oc8051, You need to first understand its memory architecture, and then track the program to the data stream.

As mentioned above, the oc8051 program and data storage are logically separated. Physically, there are four types of memory: internal program memory irom and internal data storage Iram, the external program memory is xrom, and the external data program memory is xram. The commands used to access xram are different from those used to access Iram (mov, movx, and must use dptr registers ). The storage structure used by oc8051 to control oc8051_defines.v is as follows:

　　

 1 // 2 // oc8051 ITERNAL ROM 3 // 4 `define OC8051_ROM 5  6  7 // 8 // oc8051 memory 9 //10 //`define OC8051_CACHE11 //`define OC8051_WB12 13 //`define OC8051_RAM_XILINX14 //`define OC8051_RAM_VIRTUALSILICON15 `define OC8051_RAM_GENERIC16 17 18 `define OC8051_XILINX_ROM

'Define oc8051_rom: Internal irom is used, while external xrom and oc8051 provide three optional interfaces: 1. cache; 2. Wishbone; 3. Internal signal line pass-through.

Irom and Iram belong to Part 1. xrom and xram do not exist. In actual implementation, irom and xrom only need one. Oc8051 provides an FPGA (XILINX) Implementation of irom and a behavior simulation model. All of them are in the oc8051_rom.v file and use Xilinx through 'fine oc8051_policinx_rom, otherwise, a general simulation model is used. In addition, the oc8051 project provides a tool to Convert hex files. v, the implementation of this conversion is the same as the implementation selected by 'define oc8051_xilinx_rom, and it is very inconvenient to update the code in the Rom; this is related to the ROM model used by it, the following code shows the memory model used:

 1 reg [7:0] buff [0:65535]; //64kb 2  3 assign ea = 1‘b0; 4  5 initial 6 begin 7   $readmemh("../../../bench/in/oc8051_rom.in", buff); 8 end 9 10 always @(posedge clk or posedge rst)11  if (rst)12    ea_int <= #1 1‘b1;13   else ea_int <= #1 !ea;14 15 always @(posedge clk)16 begin17   data_o <= #1 {buff[addr+3], buff[addr+2], buff[addr+1], buff[addr]};18 end

Such a storage model is hard to be directly implemented using general memory. Because 8051 is an 8-bit microprocessor, generally, the program memory bit width is 8. However, the implementation of oc8051 uses the prefetch command, three commands need to be sent at a time (the internal code can be used to verify the Code .); The model shown in the above code needs to store a program that periodically emits 4 bytes. Because the address sent by 8051 is non-aligned, such a behavior model requires the memory to support non-access to it. For example: ADDR = 1; then data_o = {buff [4], buff [3], buff [2], buff [1]}. If a 32-Bit Memory is used, 0 ~ 3 bytes are a group, 4 ~ 7 is a group. Only one group of 32-bit data can be obtained at a time.

The cache mode and WB mode and pass-through mode can be selected for external program memory interfaces. Because of the internal CPU implementation mode, the behavior model still needs to be the same as the internal program memory. The oc8051_xrom.v code is as follows:

 1 module oc8051_xrom (rst, clk, addr, data, stb_i, cyc_i, ack_o); 2  3 parameter DELAY=5; 4  5  6 input rst, clk, stb_i, cyc_i; 7 input [15:0] addr; 8 output ack_o; 9 output [31:0] data;10 11 12 reg ack_o;13 reg [31:0] data;14 15 reg [7:0] buff [0:65535];16 //reg [7:0] buff [8388607:0];17 reg [2:0] cnt;18 integer i;19 20 21 initial22 begin23 //  for (i=0; i<65536; i=i+1)24 //    buff [i] = 8‘h00;25   $readmemh("../../../bench/in/oc8051_xrom.in", buff);26 end27 28 always @(posedge clk or posedge rst)29 begin30   if (rst) begin31     data <= #1 31‘h0;32     ack_o <= #1 1‘b0;33   end else if (stb_i && ((DELAY==3‘b000) || (cnt==3‘b000))) begin34     data <= #1 {buff[addr+3], buff[addr+2], buff[addr+1], buff [addr]};35     ack_o <= #1 1‘b1;36   end else37     ack_o <= #1 1‘b0;38 end39 40 always @(posedge clk or posedge rst)41 begin42   if (rst)43     cnt <= #1 DELAY;44   else if (cnt == 3‘b000)45     cnt <= #1 DELAY;46   else if (stb_i)47     cnt <= #1 cnt - 3‘b001;48   else cnt <= #1 DELAY;49 end50 51 endmodule

It can be seen that it is basically the same as the irom behavior model, except that the parameter can define its delay period (generally, the access speed of external memory will be slower .)

PS: During the simulation today, we found that using external xrom (Reading Ea = 0 in TB: Using xrom, EA = 1: Using irom ), the interface is configured as WB interface ('define oc8051_wb). The program can run normally only when the delay parameter is defined as delay = 2. errors may occur in other settings.

Oc8051 internal logic analysis (1)