One difficult way to debug privileged students to read and write the SDRAM experiment, and finally reached.

Returning to school after the end of this year, we started to tune the SDRAM experiment in around February 19, in order to make the final Digital Photo Frame project. I read this article again, and it seems that the time sequence is the same. I also checked the information from the Internet, and the conclusion is that the two are compatible. Therefore, we do not intend to change the large timing process. I checked the program, modified the program, and tried a lot. I went down to my board for verification. I tried again and again for about 10 days, and the output was still full ff, there are other tasks, so I put it down first, but I am really upset, because this program tried its best and sincerely wanted to call it out.

Starting from January 26, August 15, I learned timequest and NIOS. I have a built-in SDRAM program for the Nias routine. The error message is varified failed in (an address), which is displayed in the system. h finds the device based on the address, which is SDRAM. Go to the Internet to find this error. One of the reasons is that the SDRAM is broken or the PIN is short-circuited. I began to doubt whether the SDRAM on my board was actually faulty. The experiment of the Integration of black gold also talked about SDRAM, so I borrowed Zhong's board, and the result program can run directly on it, but I can't do it anyway. I am not sure enough. I borrowed another board, and it can run directly! Now, we can draw a conclusion. It turns out that there is a problem with the SDRAM on my board. It is also a bitter mood that comes along with me: Isn't it because I have not been able to tune the SDRAM program for so many days at the beginning of the year? (No experience, terrible)

Then take the supporting core board and my mother board and start debugging. At the beginning of the serial port test, I found that before the program went in, the serial port assistant had received 00 at a high frequency, but this was not the case when I touched the pin on the panel by hand. I am entangled. If the program is good, how can I verify it for another reason? Yesterday, on the evening of Friday, I went back to qingyunmen and suddenly remembered that USB-to-TTL conversion was not a serial port, so I changed my mind into a small board and completely solved the problem (the solution was indeed more difficult than the problem !), I still don't know whether there is a problem with the USB-to-serial line or board grounding. This problem will be solved later. In this step, the real Debugging starts.

In fact, I have confidence in the time sequence of privilege and are more targeted at the problem because of the instructions made by netizens at http://bbs.eeworld.com.cn/thread-344070-1-1.html. The first step is to grounding udqm and LDQM. Unexpectedly, it turned out to be an experimental phenomenon of 1988. I felt deeply that at the beginning of the year, the bad SDRAM on my board had no harm to me! The next step is to add an address line. This is to expand the address by one bit. However, you should note that all relevant operations should be expanded, including moni_addr in the data_gene module, this experiment has not changed. As a result, according to 1988 netizens, we focused on finding two FIFO read/write addresses. To check whether there is any problem with the enable signal, it is necessary to read and write the program, and when the data can be written after writing the data, and when the data can be read after reading the data. This is a little time-consuming. After all, I haven't looked at the time series for half a year. Finally, I learned:

1. After the READ command is issued (the active command has been run), the CL latency is usually 2, and then the data will appear on the bus.

2. When a write command is issued (same as above), the data to be written must be synchronized with the write command on the bus.

3. trcd meaning: when sending a column read/write command, there must be an interval between the two valid commands. This interval is defined as trcd.

4. It should also be found that the counter cnt_clk_r starts from 0 when the working state of the privileged program jumps to the next state. This is also important.

Make the following changes,

Add assign sdram_udqm = 0 to the top-level file; assign sdram_ldqm = 0;

Modify assign sdram_wr_ack = (work_state = 'W _ write) in sdram_ctrl)|(Work_state = 'W _ WD) & (cnt_clk_r <9 'd8) & (cnt_clk_r> = 9 'd0); // write the response signal of the SDRAM, as the valid output signal of wrfifo

Assign sdram_rd_ack = (work_state_r = 'W _ RD) & (cnt_clk_r> = 9 'd0) & (cnt_clk_r <9 'd8 );

Modify in sdram_wr_data: else if (work_state = 'W _ write) | (work_state = 'W _ WD) & (cnt_clk <9 'd8) & (cnt_clk> = 9 'd0 )))

So far, the correct experiment results are displayed after the PIN is locked. What happened at the beginning of the year... A slight pain, but it finally came out. The entire experiment was a little eager for success, with no sigaltap or meiguang model (this is not yet learning...), and later the program will have to start with simulation, so it will be faster. But this time, the methods or improvements I thought were written on paper, just like the one in the post bar. I feel very good about this habit. I will continue to stick to it later ,~~ The manuscript is attached, leaving a memorable and excited souvenir:

 

One difficult way to debug privileged students to read and write the SDRAM experiment, and finally reached.