Achieve N-odd division with a duty cycle of 50%:
First, the rising edge is triggered to carry out the module n count, count to a value when the output clock flip, and then through (N-1)/2 again flip to get an odd n frequency clock with a non-50% duty cycle. Furthermore, when the modulo n count is triggered along the descent edge at the same time, and the selected value is the same as the trigger value of the rising edge, the output clock flip is also performed when the (N-1)/2, the output clock is flipped again to generate an odd n-frequency clock with a non-null ratio of 50%. Two N-frequency Clock Phase or operations with a duty cycle of not 50% get an odd n-frequency clock with a duty cycle of 50%.
/* Odd division, duty cycle is 50%, 5 Division */always @ (posedge CLK) // clock rising edge, Frequency Division begin if (~ RST) Begin counter2 <= 0; clk_out3p <= 0; end else begin if (counter2 = 4) Begin clk_out3p <= ~ Clk_out3p; counter2 <= 0; end else if (counter2 = 2) Begin clk_out3p <= ~ Clk_out3p; counter2 <= counter2 + 1; end else counter2 = counter2 + 1; endendalways @ (negedge CLK) // clock descent frequency begin if (~ RST) clk_out3 <= 0; else begin if (counter2 = 2 | counter2 = 4) clk_out3 <= ~ Clk_out3; endendassign clk3 = clk_out3 | clk_out3p;
[OpenGL] implements odd-number frequency division using