Computer architecture
Operator---> Register: internal operator for temporary storage of data->l1 (L1I+L1D)->l2->l3-> memory
Controller: Control memory and operator communication
Storage: memory, planar addressing
Input device and output device (IO device) and user interaction
Post:power on Self Test (power-on bootstrap)---BIOS map loads into memory---CPU reads from memory into BIOS initialization system device
Program: Instruction instruction+ data
Interrupt:cpu Knowing the IO device type via interrupt Controller
Machine language (binary)
Microcode (assembly language, chip customization), compiler-based binaries
Advanced language->api (functional interface provided by Assembly language), assembly language, binary
Hardware architecture
ARM x86 amd64 Itanium Celeron Pentium Core Corei7 Alpha Ultrasparc Power
CPU Time Shard Slice multitasking
Memory virtual address space plane address
program, load memory CPU execution--process (with life cycle)
Operating system
Hardware->kernel->system Call->libraryapi->app (Shell:cli,gui man-machine Interface)
In-memory data: Bios+kernel+app
Kernel features
Process Management memory Management hardware driver file system network functional security mechanism
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Operating System Basics