[Reprint] Build time and hold time

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The Concept of Setup and hold time can is best understood with the picture shown below.



The curve shows a clock and a data signal. The Data signal latches at the rising edge of the clock. The clock signal is in Red and Data signal are in blue.

Set up time is the amount of time before the clock edge, the input signal needs to being stable to guarantee it is accept Ed properly on the clock edge. Hold time was the amount of time after the clock edge, same input signal have to being held before changing it to make sure It's sensed properly at the clock edge.

Setup and hold Times is vigourously simulated at the Chip design level to ensure that they meet the specification. As a PCB Designer our job was to make sure that we don't deteriorate them as the clock and data signals propogate along th E PCB.

Let us assume this IC A is the source of a Clock and a Data Signal. The IC B is the destination of the Clock and the data signal. In its simplest form usually the clock and the data signals would have their length matched and and there won't change I n the setup time when the signal leaves ICS A to when it reaches B. If However, the length of the Clock Signal is much smaller than the length of the Data Signal, the setup time would get Reduced at the signals reach IC B.

Whether this would cause AQ failure would depend upon edge rate, clock frequency the setup time specification of the IC B. F or example for a clock source of 1 MHz frequecy and slow edge rate we know pretty much sure that it'll not create a Setu P time violation. For the clock source we would like to does a quick calculation as to what much mismatch is allowed. For 1 GHz clock and fast edge rates we must does calculation and take special cares as dictated by the Bus technology and TH E setup time requirements of the destination IC.

In the next chapter we'll see how to calculate the flight time of the signals as it propogates along the PCB.

[Reprint] Build time and hold time