Rom storage 1/4-cycle Sine Signal Construction DDS

Last week, the teacher asked me to write a simple DDS program. This article describes the problems I encountered and some personal thoughts throughout the process. I am new to FPGA. If you have any questions, please kindly advise ~

1. A few questions are resolved and unsolved.

Why is sine signal synthesis using ROM instead of DDS core?

In reality, if you only need to synthesize the sine signal, the DDS core is a good choice, and the DDS core can choose whether to use Taylor correction to get lower stray. Since the data in the ROM table can be selected by ourselves, using ROM for DDS is more flexible.

What is the difference between adding an icon core and A. CDC file when using chipscope?

The addition of the icon core needs to change the structure of the original program and need to be integrated again. It is precisely because this core is inside the program that we can easily select the signal to be observed;

The insert of the. CDC file does not change the program structure. You only need to re-translate the file. Because the Integrated Program is inserted, some signals will be optimized or renamed.

Is the dual-port Rom defective?

I don't know ...... The reverse center of Modelsim indicates that collision and so on cannot be simulated ...... The block ram Manual does not mention the dual-port Rom. It may be helpful to see the dual-port RAM.

2. MATLAB Simulation

Note: Because 1/4 cycles are used for storage, the value of the entire cycle must be symmetric in the center, and the value of the half-cycle must be symmetrical. This means that there should be no 0 value in the sample points.

MATLAB simulation-Rom table Storage Data

% Rom generation (unsigned number) rom_n = 2 ^ 10; % Rom table depth data_l = 14; % Rom bit width T = 1: rom_n; y = (2 ^ DATA_L-1) * (sin (2 * pI * (t-0.5)/rom_n/4); %-0.5 ensures symmetric rom_data = round (y );

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MATLAB simulation-DDS Program (please forgive me for not using case ......)

% Sine wave DDS generates f_clk = 10*10 ^ 6; % clock frequency 10mpinc_in_l = 32; % incremental length dds_clk = 10*10 ^ 3; % DDS output frequency 10kphase_in = 0; % initial phase pinc = round (dds_clk * 2 ^ pinc_in_l/f_clk); % phase increment sim_l = 4000; % simulation length phase = phase_in + pinc * (0: SIM_L-1 ); ADDR = Mod (floor (phase/2 ^ pinc_in_l * rom_n), rom_n * 4); flag = floor (ADDR/rom_n); dds_out = 1: sim_l; for I = 1: sim_l if (flag (I) = 0) dds_out (I) = rom_data (ADDR (I) + 1); else if (flag (I) = 1) dds_out (I) = rom_data (2047-addr (I) + 1); else if (flag (I) = 2) dds_out (I) =-rom_data (ADDR (I)-2048 + 1); else dds_out (I) =-rom_data (4095-addr (I) + 1); end endplot (dds_out );

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3. Explanation of DDS

The User Guide squadron DDS of Xilinx's DDS core is described in detail. This section does not repeat this content. This section describes a new DDS understanding method. This understanding method solves the problem of DDS understanding when the frequency control word is longer than the ROM table depth.

Continuous or discrete?

Continuous or discrete is what we look. As shown in, we can understand that the blue graph is discrete, while the red line is continuous. However, for the information we want to obtain, there is no difference between the two images. The sampling theorem involves ideal sampling and top sampling (sampling holding circuit). However, there is not much difference in the frequency field effect.

The Rom table stores continuous values.

According to the above theory, we can think that the ROM table stores the flat sampling result of the sine signal. As shown in (a full-cycle Rom table meets the requirements of 1/4-cycle storage)

The spectrum is mentioned in the signal and system. The above waveform can be considered as an impact function multiplied by the cycle of T, and then a window function with a width of T is accumulated. The corresponding frequency domain can be obtained. (For details, refer to flat top sampling)

Frequency Control Word

The frequency control word controls the sampling of the above step functions. If you understand this, there will be no doubt about the value of the so-called Phase Truncation Rom table. The spectrum graph can clearly present this process. However, this is not detailed here due to the inconvenience caused by the blog expression.

Here, we can explain the stray power produced by DDS.

4. Implementation of OpenGL

As the teacher taught us, the codes of OpenGL and Matlab should be exactly the same. That is to say, the program idea is named the same. But the following program is not consistent ......

'Timescale 1ns/1 psmodule dds_10k (input clk_10m, input rst, output [13:0] d_sin, output [13:0] d_cos); parameter pinc = 32' d4294967; // 10 kreg [31: 0] addr_temp = 32 'd0; Reg [9:0] addra, addrb; Reg mark_a, mark_ B; always @ (posedge (clk_10m )) // reset begin if (RST = 0) addr_temp <= 32 'd0; else addr_temp <= addr_temp + pinc; endalways @ (posedge (clk_10m )) // 1/4 begin case (addr_temp [31: 30]) 2 'b00: Begin addra <= addr_temp [29:20]; Mark_a <= 0; addrb <= ~ Addr_temp [29:20]; mark_ B <= 0; end 2 'b01: Begin addra <= ~ Addr_temp [29:20]; mark_a <= 0; addrb <= addr_temp [29:20]; mark_ B <= 1; end 2 'b10: Begin addra <= addr_temp [29:20]; mark_a <= 1; addrb <= ~ Addr_temp [29:20]; mark_ B <= 1; end 2 'b11: Begin addra <= ~ Addr_temp [29:20]; mark_a <= 1; addrb <= addr_temp [29:20]; mark_ B <= 0; end endcaseend // Rom table read rom_sin_1k18 rom_dds (. clka (clk_10m), // input clka. addra (addra), // input [9: 0] addra. douta (d_sin [12:0]), // output [12: 0] douta. clkb (clk_10m), // input clkb. addrb (addrb), // input [9: 0] addrb. doutb (d_cos [12:0]) // output [12: 0] doutb); Reg sin_mark_temp; Reg cos_mark_temp; assign d_sin [13] = sin_mark_temp; assign d_cos [13] = cos_mark_temp; // here, register is not added to the Rom, so there is a periodic latency between the output and the address. Therefore, mark must also have a periodic latency always @ (posedge (clk_10m) Begin sin_mark_temp <= mark_a; cos_mark_temp <= mark_ B; endendmodule

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Rom storage 1/4-cycle Sine Signal Construction DDS