(RPM) Memory segmentation and address calculation

Memory Segmentation and Address calculation
1. Address and content of the storage unit
In a 8086 CPU system, the memory is organized linearly in bytes. A single byte is a
Storage units, in order to identify and access each storage unit, specify a number for each storage unit, i.e.
Address of the storage unit
The address of the storage unit is represented by a binary unsigned number, starting with 0, and sequentially adding 1, then n-bit binary
Number can represent the address of a 2^n storage unit.
The information stored in a storage unit is called the contents of the storage unit. When a word is stored in the Save
Storage needs to occupy two consecutive bytes, the system stipulates: When a word stored in memory, low-byte
stored in a lower-address byte unit, high-byte storage in a higher-address byte unit,
For example, the content of the word cell in address 33451H is 5612H

_________________________00000h   
    |    ......         |
    |_______________________|33450h
    |    34h         |
    |_______________________|33451h
    |    12h         |
    |_______________________|33452h
    |    56h         |
    |_______________________|33453h
    |    29h         |
    |_______________________|
    |    ......        |
    |_______________________|

    This storage principle is called the "high and low" principle. For a two-word unit consisting of four contiguous bytes, the
also uses the same principle, such as storing data 29561234H in a double-word cell with address 33450H.

2. Segmentation of Memory
The 8086 CPU has 20 address lines, and the address space that can be addressed directly is 2^20=1m bytes, which is the storage unit
The physical address is a 20-bit binary unsigned number with a range of 00000H~FFFFFH.
However, the arithmetic logic unit within the 8086 CPU can only perform 16-bit operations, and storage units
The pointer register for address offsets (SP, BP, SI, DI, BX) are 16-bit and cannot be addressed directly to 1MB physics
Address. To do this, the 1MB address space is divided into several logical segments, each of which satisfies the following conditions:
(1) The start address of the logic segment must be a multiple of 16--related to the segment register length 16 bits
That is, the starting address of the logical segment must be 0000 for the last four bits
(2) The maximum length of the logic segment is 64k--and the pointer register is 16 bits long.

3. Calculation of Physical Address
Based on the logical segmentation of the memory, how to calculate the actual physical address? It is clear that the beginning of the logical segment
The address is a multiple of 16, that is, the starting address of the logical segment has the following form:
xxxxxxxxxxxxxxxx0000b = xxxx0h
This segment start address can be compressed to xxxxh, called the segment value, that is, the segment start address equals the segment value idiom 16.
and the storage unit to be accessed always belongs to a segment, the difference between the address of the storage cell and the starting address of the segment
is called intra-segment offset, short-term offset. Within a given segment, it is entirely possible to determine the storage unit to be accessed through an offset.
So in the entire 1MB address space,
Physical address of the storage unit = Segment Start Address + intra-segment offset
= segment Value x16 + Intra-segment offset
= Segment Value: offset (simplified representation)

After the "segment value: Offset" constitutes a logical address, the segment value is given by the register, which can be offset by the instruction pointer IP,
The stack pointer sp, and other registers that can be used as memory pointers (SI, DI, BX, BP), or directly
A 16-digit number is given. Instead of using the physical address, the logical address is used by the bus interface unit of the CPU Biu according
The segment value and offset automatically calculate the physical address.

4. Segment Register Reference
    8086 CPU has four segment registers, can maintain 4 segment value, so can use 4 segments at the same time, but four sections have division of labor.
Whenever a physical address needs to be generated, Biu automatically references a specific segment register to calculate the physical address.
    (1) when taking the instruction, Biu automatically refers to the code segment Register CS, plus the 16-bit offset of the instruction pointer IP, gets
        The physical address of the   instruction;
    (2) When a stack operation is involved, the stack segment register SS is automatically referenced, plus the SP's 16-bit offset, resulting in the
          the physical address required for the stack operation; When the offset involves a BP register, the default reference segment register is also
         Stack segment register SS;
    (3) automatically selects the Data segment Register DS or additional segment register ES when accessing the operand in memory, and then
          adds a 16-bit offset to get the physical address of the operand. The 16-bit offset at this point can be either the direct address contained in the instruction
        , or the value of a 16-bit memory pointer register, or it can be in the directive
The          offset, plus the value of the memory pointer register, depends primarily on how the instruction is addressed.

    If the segment register value is not changed, the maximum addressing range is 64KB. If a program uses a total storage length of
(including code, stack, data area) does not exceed 64K, the whole program can be used for a segment, if the code of a program
length, stack length, data is not more than 64KB, you can start at the beginning of the program to DS, SS and other segments of the Register
value If the data area of a program is longer than 64KB, the data is accessed in two or more data segments, where the
needs to change the segment value of the segment register.

Transferred from: http://blog.csdn.net/yanxiansheng/article/details/7183042

(RPM) Memory segmentation and address calculation