RTL coding Guide

1. Use functions to reduce the amount of code writing.

2. Use meaningful variable names.

3. Do not use immediate count.

4. Use a process-independent database.

5. Avoid using a hybrid clock edge. If you must use the rising and falling edges for triggering, you must ensure that the timing cycle of the module is correct in the worst case after comprehensive and time series analysis. The document description must be provided.

6 if you need to use a clock or internal clock, or reset signal, you should separate the internal clock generation circuit or reset circuit. The reset signal function is to clear all registers directly.

7. Avoid generating latches. latches may be introduced when case and if else are used.

8. Avoid generating feedback on the Combination circuit.

9. Complete sensitive vector list.

10. Pay attention to the difference between blocking and non-blocking.

11 avoid use, delay statement, full_case and parallel_case.

12 registers are used for all outputs, and registers are also used for input of each module.

13. Combine the relevant logic. The combination logic should be as close as possible to the destination register.

14. allocate parts of different design objectives to different modules.

15 avoid the use of asynchronous logic, timing exceptions (all time must be completed in one cycle as much as possible)

16 Eliminate the logic circuit of Top-layer module crosslinking.

17. Place the interface pin of the memory on the top of the IP core design.

RTL coding Guide