RX232 Serial Port sending

It is sometimes necessary to observe the variables during the commissioning of the project, and Singnatap II Logic Analyzer can only observe the pins, so it is necessary to observe the internal variables to output the variables inside. One method is to directly define the variable as a pin through the SIGNALTAP II observation, one is displayed with a display, the other is through the serial port to observe. This article mainly writes the serial port to send some code.

Timing Diagram:

Starting bit 0 data 8bit end bit 11 total 10bit

Input 50MHz is generated by Megawizard 9600Hz scale factor is 3/15625;

The code is as follows:

Module rx232_in (Input clk_50,input [7:0] datain,output reg tx,input en,output reg endtck,output clkout); wire Clk9600;reg [7:0] Temp1;reg [7:0] Temp;reg [3:0] Count=0; reg[1:0] Num=0; alt_9600 M0 (clk_50,clk9600); assign Clkout=clk9600; [Email protected] (Posedge clk9600) begin ENDTCK<=1;  Case(num)0: Beginif(EN &endtck) begin num<=1; temp<=datain;endElsenum<=0; end1: Begin tx<=0; num<=2; temp1<=Temp;end2: Begin count<=count+1;if(count<8) Begin Temp1<=temp1>>1; tx<=temp1[0];num<=2; endElseBegin endtck<=0; count<=0; num<=3; end End3: Begin tx<=1; endtck<=1; num<=0; end Endcaseend Endmodule

Verification Code:

module RX232 (input clk_50,output tx,input en,output  endtck,output CLK); wire [7:0] Datain;assign DataIn=8'haa; rx232_in M0 (CLK_50,DATAIN,TX,EN,ENDTCK,CLK); Endmodule

' Timescale 1ns/1nsmodule testbench (); reg Clk_50;reg En;wire  endtck;wire TX; RX232 M0 (. Clk_50 (CLK_50),. Tx (TX),. En,. ENDTCK (ENDTCK)); initial begin clk_50=0; en=0; # en= 1  ; end always begin #ten clk_50=! clk_50;end Endmodule

RX232 Serial Port sending