S3C2440 IIS uda134x recording and releasing

Developed by Philips, IIS (Inter-IC Sound) is a common audio device interface and is mainly used for devices such as CD, MD, and MP3.

S3C2440 has a total of five pins for IIS: iisdo, iisdi, iissclk, iislrck and cdclk. The first two pins are used for output and input of digital audio signals. The other three pins are related to the frequency of audio signals.

To make good use of IIS, you must set the signal frequency correctly. IIS is only responsible for the transmission of digital audio signals, but for the real release and recording of audio signals, additional processing chips are also needed (Here we use uda1341 ).

Iissclk is a serial clock. This line is BCK or bit clock input in the uda134x Codec Chip.

Each clock signal transmits an audio signal.

Therefore, the iissclk frequency = number of channels × sampling frequency × number of sampling digits. For example, the sampling frequency fs is 44.1 kHz and the number of sampling digits is 16 bits, if there are two channels (left and right), The iissclk frequency = 32fs = 1411.2 kHz.

Iislrck is a frame clock used to switch the left and right channels. For example, if iislrck is high, it indicates that the left channel data is being transmitted. If it is low, it indicates that the right channel data is being transmitted, therefore, the iislrck frequency should be exactly the same

Sampling frequency fs. You can clear the above two images.

Cdclk, that is, the sysclk in uda134x, can be set to system clock 256fs, 384fs or 512fs in the uda134 chip manual. Only 256fs or 384fs can be set in S3C2440. This pin is the core

The chip provides the system synchronization clock, namely the codec clock, which is mainly used for the sampling clock during audio A/D and D/A sampling.

Through the above analysis, we can find that the sampling frequency fs is critical to the frequency setting. FS is not set randomly. The value of this parameter is fixed for specific audio data, but several different fixed values are set, for example, 8 kHz, 16 kHz, 22.05 kHz, 44.1 kHz, 48 kHz, and 96 kHz. Common wav files are 44.1 kHz.

In order for the system to obtain various clock signals based on FS, it is necessary to re-adjust the system clock. S3C2440 clock sources for IIS are pclk and mpllin. Here we select pclk as the clock source for IIS. Pclk goes through two

After the pre-divider is processed, the iissclk, iislrck, and cdclk are obtained respectively (the iissclk, iislrck, and the pre-divider B obtains cdclk ).

The IIS predivider register is the iispsr ~ 9-bit pre-divider A, 0 ~ 4-bit pre-divider B. Generally, the values of the two pre-divider N are equal, that is, if you know one, the other knows, and here we

It uses cdclk to calculate the value n of the pre-divider B, that is, cdclk = pclk/(n + 1 ).

Note that FS is not directly set in the entire register group, because pclk is already set. If the value is 400 MHz, use n here to get cdclk, the relationship between cdclk and FS is also through setting the iismod register.

. So FS is determined, and then iissclk can also be set through the iismod register. If we directly use the N value and pclk value of the predivider A to calculate the iissclk and iislrck, it does not seem to provide a way.

 

When FS = 44.1 kHz, cdclk = 384fs = 16.9344 MHz. Many pclk values can be calculated based on the minimum error principle.

Mpllcon = (150 <12) | (5 <4) | 0; frequency N = 3

The error of cdclk = 16.92857 is also relatively small.

In addition, the official 2440 test bare metal file also has a set of values:

MPLLCON = (229<<12)|(5<<4)|1   N = 2<<5PCLK = 406.2857/8; CDCLK = 16.92857 

If the commonly used frequency value pclk = 50 MHz is used, there are some errors in n = 2 and cdclk = 16.666 MHz, but I can hardly hear the changes in the test sound quality. Therefore, this group is selected here.

In addition, the above two groups will cause fclk> 400 MHz. Will it cause CPU instability?

The meanings of each bit in the iiscon and iismod registers are as follows:

For the communication between the processor and uda134x, normal audio transmission is performed through IIS, as mentioned above. Configure the uda134x internal register. uda134x supports I2C and L3 bus mode configurations.

Previously, the mips architecture was set through the I2C register. Here we select the L3 bus.

Since S3C2440 does not have an L3 bus interface, we use three general I/O ports to simulate L3 to implement L3 bus transmission. Uda1341 has two modes: address mode and data transmission mode.

The address mode indicates that the address information is transmitted, and its height of 6 bits is always 000101. The lower two bits indicate the transmission mode, which is the status mode, DATA 0 mode, or data 1 mode, the status mode is mainly used to configure uda1341

The data mode is mainly used to improve the audio input and output effects. The address mode and data mode are distinguished by the l3mode line.

The code for the L3 data write mode is as follows:

The codec configuration code is as follows (corresponding to the time sequence diagram above ):

// Write function of the L3 bus interface // The input parameter data is the data to be written // The input parameter address, which indicates the address mode, 0 indicates the Data Transmission Mode Static void writel3 (byte data, byte address) {int I, j; If (address = 1) rgpbdat = (rgpbdat &~ (L3d | l3m | l3c) | l3c; // l3d = L, l3m = L (address mode), l3c = helsergpbdat = (rgpbdat &~ (L3d | l3m | l3c) | (l3c | l3m); // l3m = H (data transmission mode) for (I = 0; I <10; I ++ ); // wait for a period of time // convert parallel data to serial data output, in the order of low front and high back (I = 0; I <8; I ++) {If (Data & 0x1) // H {rgpbdat & = ~ L3c; // l3c = lrgpbdat | = l3d; // l3d = H for (j = 0; j <5; j ++ ); // wait for a while. rgpbdat | = l3c; // l3c = hrgpbdat | = l3d; // l3d = hfor (j = 0; j <5; j ++ ); // wait for a while} else // L {rgpbdat & = ~ L3c; // l3c = lrgpbdat & = ~ L3d; // l3d = Lfor (j = 0; j <5; j ++); // wait for a while rgpbdat | = l3c; // l3c = hrgpbdat & = ~ L3d; // l3d = Lfor (j = 0; j <5; j ++); // wait for a while} data >>=1;} rgpbdat = (rgpbdat &~ (L3d | l3m | l3c) | (l3c | l3m); // l3m = H, l3c = h}

// Configure uda1341writel3 (0x14 + 10,000); // status mode (000101xx + 10) writel3 (0x60, 0); //, 0: status 0, reset writel3 (0x14 + 01,000); // status mode (000101xx + 10) writel3 (0 x); //, 0: status 0, 384fs, IIS, no DC-filteringWriteL3 (0x14 +); // status mode (000101xx + 10) writel3 (0xc1, 0); //, 0, 01: Status 1,

The meaning of the codec register set above should be found in Datasheet, for example, writel3 (0xc1, 0); converting 0xc1 to binary is:
1 1 0 0 0 0 1b

The above briefly introduces the various configurations of IIS audio playback. In fact, the recording frequency should also be configured with the corresponding codec register. Here, the function of recording a piece of audio data before broadcasting is realized. We use keys for control.

Recording and playing: when the key is set to 1, the audio is stored, the recording is performed at 2, and the recording is played at 3.

Refer to previous blog posts.Qemu analog ALSA sound cardCreate a WAV file, and then convert the wav file into a C array. This step can be completed using winhex: First open the wav file to be extracted, and then

Right-click "beginning of block" at the beginning of the data section, right-click "End of block" at the end of the data section, and select the required data. Right-click "edit"-> "Copy block"-> "C source ".

The data is copied to the clipboard in the form of an unsigned char array. Next, create a new text file and paste it in. Paste it in and you will find that xinhex has already helped you define the array, you can directly use C

Code. It is quite user-friendly. This method can also be used to create Arrays for the BMP bitmap.

Code in my GitHub

Refer:

Blog.csdn.net/zhaocj/article/details/5570424

S3C2440 document

S3C2440 IIS uda134x recording and releasing