[Serialization] FPGA-based instance of the Tilde-HDL series-4-bit binary addition/subtraction counter

[Serialization] FPGA OpenGL series instances

4-bit binary addition and subtraction counter of OpenGL

I. Principles

A counter is a basic logical device used in a digital system. It not only records the number of input clock pulses, but also achieves functions such as frequency division and timing.
There are many types of counters. The pulse mode can be divided into synchronous counters and asynchronous counters. binary counters and non-binary counters can be divided into binary counters. the increase or decrease of numbers in the counting process can be divided into counter addition, counter subtraction, and reversible counter.
In this experiment, a four-digit binary addition and subtraction counter is designed. The counter can use a control signal to determine whether to add or subtract the counter. In addition, the Register also has a reset input, which is effective at a low level. There is also a signal input for loading data, used for preset data, and a C output for counter cascade. Table 1.1 shows the function list;

Table 1.1 4-bit binary addition/subtraction counter Function

II. Implementation

In the design file, enterCode

 1   /* ********* ***************************  */  
  2   
  3   'Timescale  1  NS  /     1  PS
  4   Module qu_dou (CLK, RST, A, B );
  5  
  6   Input CLK;
  7   Wire CLK;
  8   Input RST;
  9   Input;
  10   Wire;
  11   
  12   Output B;
  13  Reg B;
  14   
  15   Reg [  31  :  0  ] CNT;
  16   Reg clkout;
  17   Always @ (posedge CLK or negedge RST)
  18   Begin
  19    If  (RST  =     1  '  B0)  
  20     CNT  <=     0  ;
  21    Else  Begin  If  (  =  1  '  B1) begin  
  22       If  (CNT  > =     32  ' D3000000)  
  23     B  <=     1  ;
  24     Else   
  25   CNT  <=  CNT +     1  '  B1;  
  26     
  27   End
  28     Else  Begin B  <=    1  '  B0;  
  29     CNT  <=     0  ;
  30   End
  31   End
  32   End
 33   
  34   
  35   Endmodule 

Function implementation

 1   'Timescale  1  NS  /     1  PS
  2   
  3  Module counter4 (load, CLR, C, dout, CLK, up_down, DIN, sysclk, RST );
  4   
  5   Input load;
  6   Input CLK;
  7   Wire load;
  8   Input CLR;
  9   Wire CLR;
  10   Input up_down;
 11   Wire up_down;
  12   Input [  3  :  0  ] Din;
  13   Wire [  3  :  0  ] Din;
  14   Input sysclk;
  15  Input RST;
  16   
  17   Output C;
  18   Reg C;
  19   Output [  3  :  0  ] Dout;
  20   Wire [  3  : 0  ] Dout;
  21   Reg [  3  :  0  ] Data_r;
  22   
  23     /*  ******************** ****************  */  
  24  Wire clk_r;
  25   Qu_dou (
  26   . CLK (sysclk ),
  27   . RST (RST ),
  28   . A (CLK ),
  29   . B (clk_r ));
  30   
  31     // **************************************** *****************************  
  32     
  33   
  34   Assign dout  =  Data_r;
  35   Always @ (posedge clk_r or posedge CLR or posedge load)
  36   Begin
 37     If  (CLR  =     1  )  //  Synchronization resetting  
  38     Data_r  <=     0  ;
 39     Else     If  (Load  =     1  )  //  Synchronization preset  
  40     Data_r  <=  Din;
 41     Else  Begin  If  (Up_down  =  1  )
  42   Begin
  43     If  (Data_r  =    4  '  B1111) Begin // Add count  
  44     Data_r  <=     4  '  B0000;  
  45     C  =    1  ;
  46   End
  47     Else  Begin  //  Count reduction  
  48     Data_r  <= Data_r  +  1  ;
  49   C  =     0  ;
  50   End
  51   End
  52     Else  
  53   Begin
  54     If  (Data_r  =     4  '  B0000) Begin // Add count  
  55     Data_r  <=    4  '  B1111;  
  56     C  =     1  ;
  57   End
  58     Else Begin  //  Count reduction  
  59     Data_r  <=  Data_r  -  1  ;
  60   C  =     0 ;
  61   End
  62   End
  63   End
  64   End
  65   Endmodule