Several serial port protocol learning and finishing

First, the UART

The UART is a large family that includes interface standard specifications and bus standard specifications for RS232, RS499, RS423, RS422, and RS485. Their main difference is that their respective level ranges are different.

Embedded devices are often used in this way TTL, TTL to RS232. Common three leads: Send line TX, receive line RX, level reference ground GND.

1.1 Circuit

1.2 Communication Protocols

Each character that transmits data is transmitted one after the other.

Starting bit: A signal of logic "0" is emitted to indicate the beginning of the transmission character.

Data bit: Immediately after the start bit. The number of data bits can be 4, 5, 6, 7, 8, and so on, constituting a character. ASCII code is usually used.

Parity bit: After the data bit plus this bit, so that "1" the number of digits should be an even (even check) or odd (odd), so as to verify the correctness of data transmission.

Stop bit: It is the end of a character data flag. Can be a 1-bit, 1.5-bit, 2-bit high level.

Idle bit: In the logical "1" state, indicates that there is no data transfer on the current line.

Baud rate: The rate at which data is transferred. There are several stalls: 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 43000, 56000, 57600, 115200. Of course, you can also customize it. In both data transmission and reception, pre-unification baud rate is required in order to transmit data correctly.

Second, IIC bus

I²C (inter-integrated circuit). It has a data line SDA and a clock line SCL. The bus is connected by a pull-up resistor to the power supply. Each device connected to the I²C bus has a unique address. One of the active initiates is the host, and the other side is the slave.

1.1 Circuit

1.2 Data transfer

When there is no data transmission, the two bus is high, when the data on the IIC, its clock line SCL must be high and the SDA data must remain stable---the SDA level and SCL on the high level of "and" operation, in order to determine whether SDA is 1 or 0 When the SCL is low, the data on the SDA can be skipped.

A start signal is sent at the beginning of the data transfer; a termination signal is sent after the data transfer is completed, and an ACK is required for each 8bit data transfer. The start and end signals have master issued, and the ACK may be issued by master or slave. Transmission of data using big-endian transmission.

Start signal: SCL is high, the level of SDA from high jump to low indicates the start signal.

Termination signal: The SCL is high, and the level of SDA is signaled by a low jump to high.

1.3 Data Protocol

1.4 I²c Read and write process

Reference:

http://dpinglee.blog.163.com/blog/static/14409775320112239374615

Https://en.wikipedia.org/wiki/I%C2%B2C

Http://wenku.baidu.com/view/7c310976f46527d3240ce0e5

http://wenku.baidu.com/view/bdb46aa60029bd64783e2c6f

Three, SPI bus

The SPI (Serial peripheral Interface) is a serial serial synchronous communication protocol consisting of one master device and one or more slave devices. It has four (class) hard pin leads, SDI (serial data input), SDO (serial data output), SCK (serial shift clock), CS (chip selection). Since one master device can hang multiple slave devices, select from the device via the chip selector pin. The working clock from the device is the SCK line from the main device.

1.1 Circuit

1.2 Transmission of data

In the case of data transmission, the SPI needs to determine two things: first, whether the data is collected on the rising edge of the clock or the falling edge, and second, whether the initial (idle) state of the clock is high or low. While the idle state of I²c, the clock line is high, when data acquisition, the clock line is also high level. But the SPI gives a more liberal approach.

Cpol: The clock polarity, which indicates whether the clock signal is high or low when the SPI is idle.

Cpha: The clock phase that indicates whether the SPI device triggers data sampling when the clock signal on the SCK pin changes to a rising edge, or when the clock signal becomes a falling edge.

Then, there are two possible SPI Cpol, Cpha There are two possible, the SPI data transmission there are four possible---according to the standard, SPI data transmission has four modes.

1.3 SPI Read/write

SPI in the hardware design of the dual data-line system, according to the design, in the SPI communication process, the master-slave device will form a data ring link---Also, the main device to write data from the device once, from the device will be back to the data (as to whether the data from the device is valid, it is another---if valid, The main device reads it in, or discards it if it is not valid.

Several serial port protocol learning and finishing