Sharc DSP learning records 1---2014-07-30

Starting from today, record the details of the sharc DSP process.

 

DPI: Digital peripheral interface

Dai: digital audio interface

 

Sharc SIMD Core

SIMD single command multi-data

The ADSP-2148x contains two computing processor components used as a single command, multi-data (SIMD) engine, called Pex and Pey, each component is composed of ALU, multiplier, er and register file.

Pex is always valid. Pey can be enabled by setting the peyen mode bit of the mode1 register to 1. SIMD mode allows the processor to execute the same command in two processing components, but the processing of each processing component is not

Same data. This architecture is very effective for executing computing-intensive DSP algorithms.

 

SIMD enabled:

When any computation or data access is executed, it will be synchronized med automatically in both Processing Elements

F0 = F1 + F2; explicitly defined in source code will execute in PEX

S0 = S1 + S2; implicit operation not defined in source code will be automatically executed in Pey in the same instruction cycle

 

SIMD disabled (sisd mode ):

Only the explicit instruction will be executed in PEX

 

The width of the PM address bus is 24 bits. A maximum of 16 Mbit programs/data can be accessed.

The width of the PM data bus is 48 bits. It is used to access commands with a length of 48 characters. When used to store data, 32-Bit Single-precision floating-point numbers or 32-Bit fixed points will be in the high 32-bit

 

The 48-bit script supports a variety of parallel operations to implement concise programming. For example, a processor can perform multiplication, addition, and subtraction in two processing elements with conditions, branch at the same time, and

You can obtain up to four 32-bit data values.

 

 

 

 

Assembler analysis (FIR)

# Include "def21364.h"/* symbol definition file */

# Define taps 64/* length of filter */
# Define n 128/* number of samples */

. Extern ss_fir;

/* DM data */
. Section/DM seg_dmda;/* segments are declared in the. LDF file */
. Align 2;/* Set alignment to long-word boundary for next variable */
. Var dline [Taps + 1];/* Delay Line compensate for CIRC buffer, see comments in ss_fir.asm */
. Align 2;
. Var input [N] = "input. dat";/* array of samples */

/* PM data */
. Section/DM seg_pmda;
. Align 2;
. Var coeffs [Taps] = "ssfcoeffs. dat";/* filter coefficients */
. Align 2;
. Var output [N];/* output array */

/* PM interrupt vector Code */
. Section/PM seg_rth;
Reserved_1: Ti; NOP;
Chip_reset: idle; jump start; NOP;

/* Program memory Code */
. Segment/PM seg_pmco;

Start:
/* --------------------- Setup modify registers for arrays --------------------*/
M1 = 1;
M2 =-1;
M3 = 2;

M9 = 2;
M10 = 1;
/*----------------------------------------------------------------------------*/

 

/* --------------------- Initialization Delay Line ----------------------------*/
B0 = dline;
L0 = @ dline-1;

F8= 0.0;
Lcntr = taps, do clear_fir until lce;
Clear_fir: DM (I0, M1) = F8;

I0 = dline;
/*----------------------------------------------------------------------------*/

 

/* -------------- Setup dags for input/output/coeffs and call ss_fir ----------*/
R3 = taps;
R3 = lshift R3 by-1;/* R3 = taps/2 due to simd mode */
R0 = 3;/* 3 Macs outside of FIR Mac loop */
R3 = r3-R0;/* R3 = taps/2-3 for FIR Mac loop counter */

B1 = input;
L1 = 0;

B9 = output;
9 = 0;

B8 = coeffs;
L8 = @ coeffs;

Lcntr = N, do fir_loop until lce;
Call ss_fir (db);/* Call FIR */
F0 = DM (I1, M1);/* read one sample */
NOP;/* call can't be in last three locations of a loop */
Fir_loop: PM (I9, M10) = F8;/* Write result to output */
/*----------------------------------------------------------------------------*/

/* Terminate and wait */
Wait1: idle;
Jump Wait1;

 

 

# Include "def21364.h"/* symbol definition file */

. Global ss_fir;

/* Program memory Code */
. Section/PM seg_pmco;

Ss_fir:
Bit Set mode1 cbufen;/* circular buffer enable, one cycle effect latency */
NOP;/* circular buffering not in effect until next cycle */

S0 = DM (I0, M1);/* Move pointer to delay [1] */

Bit Set mode1 peyen;/* SIMD mode enable, one cycle effect latency */
S0 = DM (I0, m2);/* load S0 with the value of delay [1] for SIMD store, move pointer to delay [0] */

DM (I0, M3) = f0, F4 = PM (i8, M9);/* Transfer sample to delayline, done in SIMD to load end of buffer + 1 */
/* To compensate for circular buffer issue described above, read 2 coeffs */

F8 = f0 * F4, f0 = DM (I0, m3), F4 = PM (i8, M9);/* samples * coeffs, read 2 samples, read 2 coeffs */
F12 = f0 * F4, f0 = DM (I0, m3), F4 = PM (i8, M9);/* samples * coeffs, read 2 samples, read 2 coeffs */
Lcntr = R3, do Macs until lce;/* FIR loop */
Macs: F12 = f0 * F4, F8 = F8 + F12, f0 = DM (I0, m3), F4 = PM (i8, M9);/* samples * coeffs, accum, read 2 samples, read 2 coeffs */
F12 = f0 * F4, F8 = F8 + F12, S0 = DM (I0, m2);/* samples * coeffs, accum, dummy read to move pointer to oldest sample */
F8 = F8 + F12;/* Final SIMD accum */
R12 = S8;/* Move Pey total into PEX register file */

RTS (db );
Bit CLR mode1 cbufen | peyen;/* circular buffer disable, SIMD mode disable */
F8 = F8 + F12;/* Last accum */

 

Dline read/write

Red indicates the position pointed by the I0 pointer before entering the MACs loop.

 

This program uses the circular addressing method.

The numbers x of the three registers BX, lx, and IX must be consistent, while the MX registers can be randomly selected in the same Dag group.

R3 = lshift R3 by-1; // shift 1bit right