STA Analysis (v)

Parasitic parameters of the interconnect line

Typically a cell or block connection pin is called a net. In physical implementations, a net may pass through several layers of metal, because each metal layer has a different resistor and capacitance value. So, in the analysis

NET parasitic parameters (parasitics), a net is generally divided into multiple segments, each segment in a metal layer. Here's a section also called, Interconnect trace.

Resistance resistance, mainly from the trace between different metal layers and vias via.

Capacitance capacitance, also from trace, can be divided into grounded capacitance, coupling capacitance.

Inductive inductance, derived from the current loop, because the current loop in the design is generally small and short, so the inductance effect is rarely considered.

In summary, the entire interconnect parasitics is the RC distribution, generally using RC tree to model. The nodes in the RC tree are modeled with T-model or Pi-model.

T-model: The resistance R is divided into two parts, the overall structure is R/2, C, R/2.

Pi-model: The capacitance C is divided into two parts, the overall structure is C/2, R, C/2.

Wireload Models: Before floorplanning or layout, the RC is estimated by the line load model, and the interconnect length is estimated by the number of fanout.

Depending on the area, you can choose a different wireload model. such as Wld_light, Wld_conservative, wld_aggressive.

Estimate RC values According to the relationship of resistance per unit of interconnect and Cap per unit interconnect,fanout and length in Lib.

Set_wire_load_mode "Wlm_cons"-library "Lib_stdcell"

Set_wire_load_mode "Top/enclosed/segmented"

These three modes are to specify the coverage relationship of Wireload mode in hierarchy design. The top layer covers all layers underneath. Segmented is that each block is pressed to its own

The prescribed Wireload mode comes with no coverage relationship. Enclosed says the block's wireload mode is used only if a block contains exactly one net.

Default_wire_load: "Wld_light"

Wire_load_selection (WIREAREASELGRP) {

Wire_load_from_area (0,5000,wld_light);

Wire_load_from_area (5000,10000,wld_cons);}

RC Tree topology: After estimating the total value of RC, there must be a distribution of RC, and in Pre_layout, there are three species of Tree to model the same length.

The values of the best-case TREE:RC are distributed on a node so that there is no other RC on the path, and the other nodes have good parasitic parameters.

Balanced TREE:RC equivalent distribution on each node path in r/n, c/n. The RC parameters are the same on each node.

Worst-case TREE:RC are distributed on public paths so that the RC on each node is the largest.

The RC parameters prior to implement are well-estimated. After implement, you can use the tool to extract the RC parameters. Here are three types of files:

Detail Standard parasitics Format (DSPF file)

Reduced standard parasitics Format (RSPF file)

Standard Parasitics Extraction Format (spef file, there is a similar sbef file, used in binary notation, for easy tool reading. Because of the streamlined relationship, this kind of file applies more,

and easy to coupling capacitance information)

Methods to reduce parasitics in critical Net: 1) reduce the resistance. Use a wider metal, or route the trace to the upper metal layer. This will reduce the RC.

2) Increase the space between the traces, which can reduce coupling capacitance.

3) for correlated nets, such as the data bus for DDR, net cabling is best in the same metal.

STA Analysis (v)