Static timing Analysis---timing path

The Time series analysis tool finds and analyzes all paths in the design. Each path has a starting point (startpoint) and an end point (endpoint). The starting point is the point at which the data in the design is loaded by the clock, and the end point is the time at which the data is loaded by another time along the combined logic.

The starting point in the path is the clock pin of a timing element or the design of input port. Input port can be used as a starting point because the data can be entered into the design by an external source (external source).

The end point is the data entry pin for the timing element or the output port of the design. Similarly, output port can be used as an end point because the data can be snapped to by an external source.

Shows an example of a time series path.

The path1 starts at a input port and ends at the data input of the timing element

Path2 starts at the clock pin of the timing element and ends at the data input of the timing element

The path3 starts at the clock pin of the timing element and ends in an output port

Path4 starts at input port and ends at output port

Each path has its own slack,slack value that can be positive, 0, or negative. A path with the worst slack is called critical path.

Critical path has the largest negative slack value. If all paths do not have a timing violation, then slack are positive, and the smallest slack is critical path.

Complex critical paths means that the path of a group is critical path.

Paths can be grouped (group) to get their own timing analysis, timing reporting, and optimization.

The timing report can be obtained by entering report_timimg in the IC Compliler, as shown below.

startpoint:i_risc_core/i_instrn_lat/instrn_1_reg_27_ (Rising edge-triggered flip-flop clocked by SYS_2X_CLK) Endpoint:i_risc_core/i_alu/Zro_flag_reg (Rising edge-triggered flip-flop clocked by SYS_2X_CLK) Path Group:sys_2x_clkpath Type:max
Point INCR Path----------------------------------------------------------------------------------clock SYS_2X_CLK (Rise edge)0.00                0.00Clock Network delay (propagated)0.51                0.51I_risc_core/I_INSTRN_LAT/INSTRN_1_REG_27_/CP (SENRQ1)0.00                0.51Ri_risc_core/i_instrn_lat/instrn_1_reg_27_/q (SENRQ1)0.62                1.13Fi_risc_core/i_instrn_lat/instrn_1[ -] (Instrn_lat)0.00                1.13Fi_risc_core/i_alu/alu_op[3] (ALU)0.00                1.13Fi_risc_core/I_ALU/U288/ZN (NR03D0)0.36*1.49Ri_risc_core/I_ALU/U261/ZN (ND03D0)0.94*2.43Fi_risc_core/I_ALU/U307/ZN (INVBD2)0.35*2.78Ri_risc_core/i_alu/u343/z (AN02D1)0.16*2.93Ri_risc_core/I_ALU/U344/ZN (NR02D0)0.11*3.04Fi_risc_core/I_ALU/U348/ZN (ND03D0)0.28*3.32Ri_risc_core/I_ALU/U355/ZN (NR03D0)0.29*3.60Fi_risc_core/i_alu/u38/z (AN02D1)0.15*3.75Fi_risc_core/i_alu/u40/z (AN02D1)0.12*3.87Fi_risc_core/I_ALU/U48/ZN (ND02D1)0.06*3.93Ri_risc_core/I_ALU/U27/ZN (ND02D1)0.06*3.99Fi_risc_core/I_ALU/ZRO_FLAG_REG/D (SECRQ4)0.00*3.99Fdata Arrival Time3.99

clock SYS_2X_CLK (Rise edge)4.00                4.00Clock Network delay (propagated)0.47                4.47Clock Uncertainty-0.10                4.37I_risc_core/I_ALU/ZRO_FLAG_REG/CP (SECRQ4)0.00                4.37rlibrary Setup time-0.37                4.00Data Required time4.00--------------------------------------------------------------------------------Data Required time4.00Data Arrival Time-3.99-------------------------------------------------------------------------------Slack (MET)0.01

The diagram for this example is as follows:

The report starts by showing the starting point of the path, the path end point, the path group name, and the type of path detection. In this example, the path detection type is Max, which means the maximum delay or setup check, if min is the smallest delay or hold check

The following large table shows the delay value of points from the starting point to the end point. The columns have three identities, point, incr, and path, each representing the points in the path, the delay required for this point, and the delay value that accumulates from the start point to this point.

An asterisk (*) indicates that the delay value in the SDF file is used, and R and F indicate a rising or falling edge.

It was previously said that the path starts with the clock along the data load and ends at the data input of the device. The data arrival time in the table indicates how long it takes to arrive from the loading clock along to the end point.

The slack value is obtained by subtracting arrival time from required.

The slack shown in the example is very small, which means that the timing constraints are very reluctant to meet the requirements. A negative number would need to be redesigned to fix the violation, such as using a larger drive strenth driver to reduce net delay.

Conversely, if the slack value is quite large, then there are many opportunities for optimization in this path. For example, a smaller and slower driver to reduce the area, or a higher threshold of driver to reduce leakage power.

Static timing Analysis---timing path