Stm32 's learning memory and bus architecture

Four drive units: the D-bus bus and S-bus bus for the CONTEXT-M3 core, the Universal DMA1, and the general purpose DMA2.

Four driven units: internal Flash (internal Mountain village memory), internal SRAM, FSMC, AHB to APB Bridge Ahp2apbx.

The Icode bus is the bus that connects the CONTEXT-M3 to the internal Flash Flash instruction interface, realizing the prefetch function of the instruction.

The Dcode bus is a bus that connects the CONTEXT-M3 with the internal Flash memory (Flash) data interface to enable data reading.

The system bus connects the CONTEXT-M3 and bus matrices, and the bus matrix coordinates the access between CONTEXT-M3 and DMA.

The DMA bus implements the connection of the DMA AHB Master Interface Channel bus interface.

Bus matrix
This bus matrix coordinates the access quorum between the kernel system bus and the DMA Master bus. This quorum utilizes the rotation algorithm. This bus matrix consists of four drive components (CPU Dcode, System bus, DMA1 bus, and DMA2 bus) and four passive components (Flash memory Interface (FLITF), SRAM, FSMC, and AHB2APB bridges).
The AHB peripheral is connected to the system bus via a bus matrix, allowing DMA access.

APB1 operating speed is limited to 36MHZ,APB2 operation at full speed (up to 72MHz).

Memory Organization
Program memory, data memory, registers, and input and output ports are organized in the same 4GB linear address space.
Data bytes are stored in a small-ended format in memory. The lowest address byte in a word is considered to be the lowest valid word in the word.

flash/code Area 512M, on-chip sram512m, on-chip peripheral/Register area 512M. Other address spaces within 4G are reserved address spaces.