Stm32 Advanced Timer 1 configuration note __stm32f103 Basic Peripherals Configuration

void Tim1_int_init (U16 arr,u16 PSC) {tim_timebaseinittypedef tim_timebasestructure; Nvic_inittypedef nvic_initstructure; Rcc_apb2periphclockcmd (RCC_APB2PERIPH_TIM1, ENABLE); ① clock TIM1 enable//timer TIM1 Initialize tim_timebasestructure.tim_period = arr; Set the value of the automatic reload register period Tim_timebasestructure.tim_prescaler =PSC; Set the clock frequency divisor prescaler frequency value tim_timebasestructure.tim_clockdivision = TIM_CKD_DIV1; Set clock partition Tim_timebasestructure.tim_countermode = tim_countermode_up; TIM up Count tim_timebasestructure.tim_repetitioncounter=0; The Advanced Timer 1 is configured with a timer function that can be the normal counting frequency of the 72MHz noteworthy place Tim_timebaseinit (TIM1, &tim_timebasestructure); ② Initialization of TIM1 tim_itconfig (tim1,tim_it_update,enable); ③ allow update interrupt//Interrupt priority NVIC setting Nvic_initstructure.nvic_irqchannel = TIM1_UP_IRQN; TIM1 interrupt nvic_initstructure.nvic_irqchannelpreemptionpriority = 0; Priority 1 First Class nvic_initstructure.nvic_irqchannelsubpriority = 3; From priority level 3 Nvic_initstructure.nvic_irqchannelcmd = ENABLE; IRQ channels are enabled to Nvic_init (&nvic_initstructure); ④ initializes the NVIC register Tim_cmd (TIM1, ENABLE); ⑤ to enable TIM1}


void Tim1_up_irqhandler (void)//tim1 break {if (Tim_getitstatus (TIM1, tim_it_update)!= RESET)//Check TIM1 update interrupt occurrence {Tim_clea Rflag (TIM1, tim_it_update); Clear TIM1 Update Interrupt flag led1=! LED1; The red word above must be noted because the advanced timer is four more than a general-purpose timer:



By the way. Configuration of a general-purpose timer: void Tim4_int_init (U16 arr,u16 PSC) {tim_timebaseinittypedef tim_timebasestructure; Nvic_inittypedef nvic_initstructure;
Rcc_apb1periphclockcmd (RCC_APB1PERIPH_TIM4, ENABLE); Clock enables//timer TIM4 initialization tim_timebasestructure.tim_period = arr; Sets the value of the automatic reload register period for the next update event mount activity Tim_timebasestructure.tim_prescaler =PSC; Set the Prescaler frequency value tim_timebasestructure.tim_clockdivision = Tim_ckd_div1 for the timx clock frequency divisor; Set Clock split: Tdts = Tck_tim Tim_timebasestructure.tim_countermode = tim_countermode_up; TIM up-count mode Tim_timebaseinit (TIM4, &tim_timebasestructure); Initializes the TIMX time base unit Tim_itconfig (Tim4,tim_it_update,enable) based on the specified parameters; Enables TIM4 interrupts to be specified, allowing updates to be interrupted
Interrupt Priority NVIC Setting Nvic_initstructure.nvic_irqchannel = TIM4_IRQN; TIM3 interrupt nvic_initstructure.nvic_irqchannelpreemptionpriority = 0; Priority 0 First Class nvic_initstructure.nvic_irqchannelsubpriority = 3; From priority level 3 Nvic_initstructure.nvic_irqchannelcmd = ENABLE; IRQ channels are enabled to Nvic_init (&nvic_initstructure); Initializing Nvic Registers

Tim_cmd (TIM4, ENABLE); Enable TIMX}//Timer 4 Interrupt Service program void Tim4_irqhandler (void)//tim3 Interrupt {if (Tim_getitstatus (TIM4, tim_it_update)!= RESET)/check TIM4 more Whether the new interrupt occurs {tim_clearitpendingbit (TIM4, tim_it_update);//Clear TIMX update interrupt flag led0=! LED0; Get_angle (); } }