STM32 Interrupt Priority level

M3 with 8bits and STM32 with high four bits to represent preemption and sub-priority: Bit=1 for preemption, bit=0 for non-preemption that is sub-priority, so there are 5 scenarios in the group:

Description of the grouping Bit7 Bit6 Bit5 BIT4:

Group No. 0 0 0 0 0

Group 1th 1 0 0 0

Group 2nd 1 1 0 0 preemption Total 2^2=4 (0~3), sub-priority 2^2=4 (0~3), total 4*4=16 level nesting

Group 3rd 1 1 1 0 preemption Total 2^3=4 (0~7), sub-priority 2^1=2 (0~1), total 8*2=16 level nesting

Group 4th 1 1 1 1

Who is the priority: the smaller the number, the higher the priority, the smaller the preemption-level number, the larger

1 preemption is the same, sub-priority is different: no preemption deprivation at this time, sorted by sub-priority order

2 preemption and sub-priority are the same but have successively: at this time no preemption deprivation, according to FIFO, the previous implementation of the latter can be done;

3 preemption and sub-priority are the same and arrive at the same time: order by interrupt vector table

STM32 Interrupt Priority level