Storage Systems (2)-------Cache

Tag: BSP color write style update CPU random byte ack

1. Purpose

　　Solve the problem of CPU and main memory speed mismatch.

2. Working principle

The CPU issues the address of the visit. Address format is the primary save address format.

The address is accepted at the same time as the cache and main memory. The cache is accepted by an address mapping and transformation mechanism to determine whether a hit is available.

If hit, fetch the data directly from the cache;

If missing, extracts data from main memory and loads the data into the cache. (If the cache space is insufficient, design the replacement policy)

The exchange of data between the CPU and cache and main memory in words/bytes

The exchange of data between the cache and main memory in block units

3. Address mapping:

　Full-linked mappings, direct mappings, group-linked mappings

1). Full-linked mappings

? Random mapping between main memory and cache block

? Maximum flexibility, highest cache utilization and highest cost

? Main memory address = block Address (high m bit) + in-block address (low n bits)

Cache address = block Address (high C-bit) + in-block address (low n-bit)

? Catalog table Record mapping relationship:

Main memory block number-cache block number-valid bit

2). Direct mapping

? Main memory block mapped to cache fixed block, main memory according to cache size partition, the number of blocks in the same area. Mapping Relationship: j = i% 2^c

? Simple, fast. Not flexible

? Main memory address = area code (High T-bit) + area block number (middle C bit) + in-block address (low n-bit)

Cache address = block Address (high C-bit) + in-block address (low n-bit)

? Zone table Record mapping relationship:

Area code-Valid bit

? remarks

? main memory block I transfer into cache block I

The main memory is the same as the cache block number, so that when you register the area table, you only need to record the block area

The Address block Number field stores block number I, and the area code is removed from the I-store word (for cache block I) in the zone table, compared to the address Area Code field.

The cache total 2^c block, the zone table altogether 2^c the storage word

3). Group-Linked Mappings

? Main memory by cache size partition, and cache by the same large cell grouping, the same number of blocks within the group. Direct mapping between groups, intra-group full-linked mappings.

? Main memory address = area code (s bit) + group number (U bit) + Group Inner block number (V ' bit) + in-block address (low n-bit)

Cache address = Group number (U bit) + Group Inner block number (v bit) + block address (low n bits)

? Block table record mapping relationship:

Area code-group number-block number in group-valid bit

? remarks

The area code group number together as a judgment hit flag

4. Replacement algorithm

1). When the cache has no space, replace the old block and load the new block.

2).

? Random algorithm (RAND method):

Random substitution regardless of block usage

Easy to implement, fast. Reduce hit rate and cache productivity.

?FIFOmethod:

Regardless of block usage, the advanced person is replaced first.

Load block count is 0, other block count plus one, replacement count Max

? Least recently unused (LRU):

? Most infrequently used (LFU):

When replaced, all counters are zeroed

Minimum replacement count

5. Write Back Policy

1). ensure consistency :

CPU write cache, not write main memory;

I/O write main memory, to write cache in time.

2). Write Policy:

? write Direct (through)

Write cache at the same time write main memory;

Frequent visits to reduce average time to visit

Use non-write allocation method (cache miss, write main memory only)

? Writeback method (write back)

Simple writeback (regardless of update, write back), flag bit writeback (write back only updated blocks)

Use the Write allocation method (cache misses, write main memory, load cache)

Storage Systems (2)-------Cache