Three-Stage state machine [CPLD/FPGA]

The composition of the state machine is actually relatively simple, and there are roughly three elements:Input, output, and status.

The key to state machine description is to clearly describe the elements of the previously improved state machines, that isHow to perform status transfer; what is the output of each status; whether the status transfer is related to the input conditions.

Some people are used to writing the entire state machine into an always module. In this module, both State Transfer and State input and output are described. This method is generally called the FSM description method;
Another method is to use two always modules. One of the always modules describes State Transfer in synchronous time sequence, and the other uses combined logic to judge state transfer and describe the state transfer rule.
It is called the two-stage FSM description; another one is developed based on the two-stage, which uses three always modules and one always module uses synchronous time series to describe state transfer;
The two use the combined logic to determine the State Transfer Condition and describe the state transfer rule. The third always module uses the synchronous timing circuit to describe the output of each State.

The last two methods are generally recommended, that is, two-step and three-step. The reason is: Like other designs, it is best to use synchronization timing to improve design stability and eliminate glitches. Status transfer is generally the same
The State Transfer Condition of the Step timing circuit is the combination logic. The reason why the two stages are more reasonable than one stage is that it places the time series logic and the combination logic into different always.ProgramFast implementation, this
It is easy to understand and read.CodeTo facilitate you to add appropriate time series constraints, and facilitate the design of the layout manager.

In the two stages, the output of the current State is implemented by the combination logic. Such implementation may produce burrs, which is not conducive to constraints. For the same reason, in some designs that require the introduction of output feedback, the two sections introduce the feedback of the combination logic to make the overall failure, which must be avoided.

Compared with the two-phase clock, the key is to determine the output of the current State based on the input conditions in the previous state based on the state transfer rule, so that no additional clock cycle is introduced, registers are output.

A three-stage state machine is roughly as follows:

 Module State (nrst, CLK, sig1, sig2, out1, out2 );
Input Nrst, CLK;
 Input Sig1, sig2;
 Output Out1, out2;
 Reg Out1, out2;
 Reg [ 2 : 0 ] NS, Cs;
 Parameter [ 2 : 0 ]
Idle = 3  ' B000,  
 S1 = 3  '  B001,  
 S2 = 3  '  B010;  
  
//  First, status transition  
  Always @( Posedge CLK Or  Negedge Nrst)
 If (! Nrst)
CS <= idle;
 Else 
CS <= ns;
 
//  Section 2, combined logic judgment  
  Always @ (Nrst Or CS Or Sig1 Or Sig2)
 Begin 
NS =3  '  BX; // Default Value  
            Case (CS)
Idle: Begin 
 If (Sig1....) NS = idle;
 Else NS = S1;
 End 
S1: Begin 
 If (...) NS = S1;
 Else NS = xxxx;

S2 :.....
 Endcase 
 End 
 
//  Section 3: FSM output  
  Always @( Posedge CLK Or   Negedge Nrst)
 If (! Nrst)
{Out1, out2} <= 2  ' B00;  
  Else 
 Begin 
{Out1, out2} <= 2  '  B00;  
     Case (NS)
Idle :......

S1:
 Endcase 
 End 
 Endmodule 

 

In fact, the two sections combine the second and third sections.

 The three-stage writing method can be summarized as follows:

 

Note: Use <= in the third section and use = in the second section.