Timequest 3 ------

Clock skew = <destination Reg clock delay>-<source Reg clock delay>

In order to overlay the impact of clock skew on data delay, the following three formulas (for fpga2ic) are given ):

1. clock skew = <ext_clk delay>-<fpga_clk delay>

2. Data delay' = <data delay>-<clock skew>

 

For multi-Bit Width data (take three digits as an example): In D [0] ~ D [2] in the three single-digit width, delay Max affects the establishment time (establishing the relationship), and delay min affects the retention time (maintaining the relationship ).

Timequest is analyzing d [0 .. 2] when setting up a time, you only need to pay attention to the "Most Dangerous Building time". Logically, nothing is more dangerous than "the most dangerous. In the same way, timequest is analyzing d [0 .. 2] When holding time, it only needs to pay attention to the "most dangerous holding time", because nothing is more dangerous than "the most dangerous.

 

The formula is derived based on FPGA. Therefore, the fpga2ic formula is also called the output formula. The output formula for the starting edge is also called the output max, and the output formula for the next starting edge is also called the output Min.

Out max = <fpga2ext delay max>-<clock skew> + ext_tsu;

Out min = <fpga2ext delay min>-<clock skew>-ext_th;

Ic2fpga is an external model for reading data from an IC. However, no matter how the location changes, it is basically the same,

Input max = <ext2fpga delay max>-<clock skew> + ext_tco;

Input min = <ext2fpga delay min>-<clock skew> + ext_tco;

 

Set_input_delay:

Set output delay and set input delay are like "outsourcing materials". First, we collect various external delay information and package it in an "outsourcing materials". Then, we discard it to timequest. Of course, timequest knows that a certain delay Max is for establishing a link, and another certain delay Min is for maintaining a link.

Set_ioutput_delay:

Timequest analyzes the internal setup and hold timing sequence by referring to the information of "outsourcing materials"... in this way, timequest can separately separate the external and internal delay information.

 

For the physical clock, delay max (late) will create the minimum build time, and the change of delay min (early) will create the minimum build time.

Timequest 3 ------