Timing process of SPI bus protocol

SPI bus is used in many aspects. Now we will explain the specific process of SPI bus protocol. The following is an example of a specific timing problem. We hope that the introduction in this article will help you master this part of knowledge.

The SPI bus protocol is a ring bus structure consisting of sscs, sck, sdi, and sdo. Its timing is actually very simple, mainly under the control of sck, two two-way shift registers for data exchange. Assume that the following 8-bit registers are installed with 10101010 of the data to be sent, and the rising edge sends, the falling edge receives, and the High Level sends the data first. When the first rising edge comes, the data will be sdo = 1; register = 0101010x. When the descent edge arrives, the level on sdi will be stored in the register, then the register = 01010sdi, so that after 8 clock pulses, the content of the two registers is exchanged once. In this way, an spi sequence is completed.

Example:

Assume that the host and slave are ready for initialization: And the sbuff of the host is 0xaa, And the sbuff of the slave is 0x55, the following shows the eight clock periods of the SPI bus protocol in a step-by-step manner: assume that the rising edge sends data.

 
 

  
  
Pulse host sbuff slave sbuff sdi sdo
  
  
0 10101010 01010101 0 0
  
  
1 up to 0101010x1010101x0 1
  
  
1 under 01010100 10101011 0 1
  
  
2. 1010100x0101011x1 0
  
  
2 lower 10101001 01010110 1 0
  
  
3. 0101001x1010110x0 1
  
  
3 lower 01010010 10101101 0 1
  
  
4 up to 1010010x0101101x1 0
  
  
4 lower 10100101 01011010 1 0
  
  
5 up to 0100101x1011010x0 1
  
  
5 lower 01001010 10110101 0 1
  
  
1001010x0110101x1 0 on 6
  
  
6 lower 10010101 01101010 1 0
  
  
0010101x1101010x0 1 on 7
  
  
00101010 11010101 0 1 under 7
  
  
0101010x1010101x1 0 on 8
  
  
8 lower 01010101 10101010 1 0
 
 

In this way, the eight-bit switching of two registers is completed. The above indicates the rising edge, the lower indicates the falling edge, and sdi and sdo are relative to the host. When the ss pin is used as the host, the slave can passively select it as the slave, and the slave can be used as the slice pin. According to the above analysis, a complete transmission cycle is 16 bits, that is, two bytes, because the host must first send commands and then prepare data from the host based on the host name, the Host reads the data back in the next 8-bit clock cycle.

The SPI bus is a three-line synchronous interface launched by Motorola for Synchronous Serial Communication: A clock line SCK, a data input line MOSI, and a data output line MISO; it is used for full-duplex and synchronous serial communication between the CPU and various peripheral devices. The main features of the SPI bus protocol include: it can send and receive serial data at the same time; it can work as a host or slave machine; it provides a programmable clock frequency; it can send an end interrupt sign; and write conflict protection; bus competition protection.

To exchange data with peripherals, the SPI module outputs serial synchronization clock polarity and phase which can be configured according to the working requirements of peripherals. The clock polarity CPOL has no significant impact on the transmission protocol. If CPOL = 0, the idle status of the serial synchronization clock is low. If CPOL = 1, the idle status of the serial synchronization clock is high. Clock Phase CPHA) can be configured to select one of two different transmission protocols for data transmission. If CPHA = 0, the first hop of the serial synchronization clock goes up or down) data is sampled; If CPHA = 1, data is sampled when the second hop along the rise or fall of the serial synchronization clock. The SPI main module and the peripheral sound Clock Phase and polarity of the communication should be consistent.

Design of SPI function module

According to the function definition and the working principle of SPI, the entire IP Core is divided into eight sub-modules: uC interface module, clock division module, data transmission FIFO module, data receiving FIFO module, state machine module, data sending logic module, data receiving logic module, and interrupt form module.

In-depth analysis of the four transmission protocols of the SPI bus protocol shows that the other three protocols can be obtained by converting the serial synchronous clock. To simplify the design, If You Want To transmit multiple data in a row, insert a serial clock to idle wait between two data transmissions, so that the state machine only needs two statuses of idle and working) it will work correctly.