u-boot-2016.11 Transplant Uboot-spl.bin

First, clock initialization 1, modify Clock.h CD Arch/arm/mach-s5pv210/include/mach/vim clock.h/* Add by Sourcelink */struct S5pv210_clock {
        unsigned int apll_lock;
        unsigned char res1[0x04];
        unsigned int mpll_lock;
        unsigned char res2[0x04];
        unsigned int epll_lock;
        unsigned char res3[0x0c];
        unsigned int vpll_lock;
        unsigned char res4[0xdc];
        unsigned int apll_con0;
        unsigned int apll_con1;
        unsigned int mpll_con;
        unsigned char res5[0x04];
        unsigned int epll_con0;
        unsigned int epll_con1;
        unsigned char res6[0x08];
        unsigned int vpll_con;
        unsigned char res7[0xdc];
        unsigned int clk_src0;
        unsigned int clk_src1;
        unsigned int clk_src2;
        unsigned int clk_src3;
        unsigned int clk_src4;
        unsigned int clk_src5;
        unsigned int clk_src6;
       unsigned char res8[0x64]; unsigned int clk_src_mask0;
        unsigned int clk_src_mask1;
        unsigned char res9[0x78];
        unsigned int clk_div0;
        unsigned int clk_div1;
        unsigned int clk_div2;
	unsigned int clk_div3;
        unsigned int clk_div4;
        unsigned int clk_div5;
        unsigned int clk_div6;
        unsigned int clk_div7;
        unsigned char res10[0x24];
        unsigned int clk_gate_sclk;
        unsigned char res11[0x18];
        unsigned int clk_gate_ip0;
        unsigned int clk_gate_ip1;
        unsigned int clk_gate_ip2;
        unsigned int clk_gate_ip3;
        unsigned int clk_gate_ip4;
        unsigned char res12[0x0c];
        unsigned int clk_gate_block;
unsigned int clk_gate_ip5;

};

        2. Add clock initialization function CD Board/samsung/smdkv210/vim smdkv210.c void Clock_init (void) {u32 val = 0;

        struct S5pv210_clock *const clock = (struct S5pv210_clock *) samsung_get_base_clock ();/* 1. Set PLL lockout value */Writel (0xFFFF, &clock->apll_lock);
        Writel (0xFFFF, &clock->mpll_lock);
        Writel (0xFFFF, &clock->epll_lock);

        Writel (0xFFFF, &clock->vpll_lock);                  /* 2. Set the PMS value of the PLL (using the values recommended by the chip manual) and enable the PLL */* P M S EN */Writel ((3 << 8) | (<< 16) | (1 << 0) |      (1 <<), &clock->apll_con0); /* FOUT_APLL = 1000MHz */Writel (<< 8) | (667 << 16) | (1 << 0) |       (1 <<), &clock->mpll_con); /* FOUT_MPLL = 667MHz */Writel ((3 << 8) | (<< 16) | (2 << 0) |      (1 <<), &clock->epll_con0); /* FOUT_EPLL = 96MHz */Writel ((6 << 8) | (108 << 16) | (3 << 0) |       (1 <<), &clock->vpll_con); /* FOUT_VPLL = 54MHz */* 3. Wait for PLL lock */while (!) Readl (&clock->apll_coN0) & (1 << 29)); while (!) (
        Readl (&clock->mpll_con) & (1 << 29)); while (!) (
        Readl (&clock->apll_con0) & (1 << 29)); while (!) (
        Readl (&clock->epll_con0) & (1 << 29)); while (!) (

        Readl (&clock->vpll_con) & (1 << 29)); /* * * 4. Set the system clock source, select PLL for clock output */* Mout_msys = SCLKAPLL = FOUT_APLL = 1000MHz * * Mout_dsys = SCLKMP
                                                                                                                             LL = FOUT_MPLL = 667MHz * * Mout_psys = SCLKMPLL = FOUT_MPLL = 667MHz * * Onenand = Hclk_psys */ Writel ((1 << 0) | (1 << 4) | (1 << 8) |

        (1 <<), &AMP;CLOCK-&GT;CLK_SRC0);     /* 4. Set the clock source for other modules */* 6. Set the system clock divider value */val = (0 << 0) |
                       /* Apll_ratio = 0, freq (ARMCLK) = Mout_msys/(apll_ratio + 1) = 1000MHz */ (4 << 4) |     /* A2m_ratio = 4, freq (A2M) = SCLKAPLL/(a2m_ratio + 1) = 200MHz */(4 << 8) | /* Hclk_msys_ratio = 4, freq (hclk_msys) = ARMCLK/(hclk_msys_ratio + 1) = 200MHz */(1 << 1     2) | /* Pclk_msys_ratio = 1, freq (pclk_msys) = Hclk_msys/(pclk_msys_ratio + 1) = 100MHz */(3 <&lt ; 16) | /* Hclk_dsys_ratio = 3, freq (Hclk_dsys) = Mout_dsys/(hclk_dsys_ratio + 1) = 166MHz */(1 <&lt ; 20) |  /* Pclk_dsys_ratio = 1, freq (pclk_dsys) = Hclk_dsys/(pclk_dsys_ratio + 1) = 83MHz */(4 <<     24) | /* Hclk_psys_ratio = 4, freq (hclk_psys) = Mout_psys/(hclk_psys_ratio + 1) = 133MHz */(1 <&lt ;      28); /* Pclk_psys_ratio = 1, freq (pclk_psys) = Hclk_psys/(pclk_psys_ratio + 1) = 66MHz */Writel (Val, &clock->

        CLK_DIV0); /* 7. Set the clock divider value for other modules */} II, DDR initialization 1, add DMC Register CD arch/arm/mach-S5pv210/include/mach/vim dmc.h/* Add by Sourcelink */#ifndef __asm_arm_arch_dram_h_ #define __asm_arm_arch_dram_h_
        #ifndef __assembly__ struct S5PV210_DMC0 {unsigned int concontrol;
        unsigned int memcontrol;
        unsigned int memconfig0;
        unsigned int memconfig1;
        unsigned int directcmd;
        unsigned int prechconfig;
        unsigned int phycontrol0;
        unsigned int phycontrol1;
        unsigned char res1[0x08];
        unsigned int pwrdnconfig;
        unsigned char res2[0x04];
        unsigned int timingaref;
        unsigned int timingrow;
        unsigned int timingdata;
        unsigned int timingpower;
        unsigned int phystatus;
        unsigned int chip0status;
        unsigned int chip1status;
        unsigned int arefstatus;
        unsigned int mrstatus;
        unsigned int phytest0;
unsigned int phytest1;

}; struct S5PV210_DMC1 {unsignedint Concontrol;
        unsigned int memcontrol;
        unsigned int memconfig0;
        unsigned int memconfig1;
        unsigned int directcmd;
        unsigned int prechconfig;
        unsigned int phycontrol0;
        unsigned int phycontrol1;
        unsigned char res1[0x08];
        unsigned int pwrdnconfig;
        unsigned char res2[0x04];
        unsigned int timingaref;
        unsigned int timingrow;
        unsigned int timingdata;
        unsigned int timingpower;
        unsigned int phystatus;
        unsigned int chip0status;
        unsigned int chip1status;
        unsigned int arefstatus;
        unsigned int mrstatus;
        unsigned int phytest0;
unsigned int phytest1;

};
                                                                                     #endif #endif                                               
2. Add DDR initialization function CD Board/samsung/smdkv210/vim smdkv210.c void Ddr_init (void
        {struct S5PV210_DMC0 *const dmc0 = (struct s5pv210_dmc0 *) samsung_get_base_dmc0 ();

        struct S5PV210_DMC1 *const dmc1 = (struct S5PV210_DMC1 *) samsung_get_base_dmc1 ();
        /* DMC0 */Writel (0x00101000, &dmc0->phycontrol0);                 Writel (0x00101002, &dmc0->phycontrol0);
        /* DLL on */Writel (0x00000086, &dmc0->phycontrol1);                 Writel (0x00101003, &dmc0->phycontrol0);         /* DLL start */while ((Readl (&dmc0->phystatus) & 0x7)! = 0x7);                  /* Wait DLL locked */Writel (0x0fff2350, &dmc0->concontrol);                  /* Auto Refresh Counter should be off */Writel (0x00202430, &dmc0->memcontrol);

        /* Dynamic power down should is off */Writel (0x20e01323, &AMP;DMC0-&GT;MEMCONFIG0); Writel (0xFF000000, &dmc0->prechconfig);

        Writel (0XFFFF00FF, &dmc0->pwrdnconfig);                  Writel (0x00000618, &dmc0->timingaref);
        /* 7.8us * 200MHz = 1560 = 0x618 */Writel (0x19233309, &dmc0->timingrow);
        Writel (0x23240204, &dmc0->timingdata);

        Writel (0x09c80232, &dmc0->timingpower);                   Writel (0x07000000, &dmc0->directcmd);                   /* NOP */Writel (0x01000000, &dmc0->directcmd);                   /* PALL */Writel (0x00020000, &dmc0->directcmd);                   /* EMRS2 */Writel (0x00030000, &dmc0->directcmd);                   /* EMRS3 */Writel (0x00010400, &dmc0->directcmd);                   /* EMRs Enable DLL */Writel (0x00000542, &dmc0->directcmd);                   /* DLL Reset */Writel (0x01000000, &dmc0->directcmd); /* PALL */Writel (0x05000000, &dmc0->dirEctcmd);                   /* Auto Refresh */Writel (0x05000000, &dmc0->directcmd);                   /* Auto Refresh */Writel (0x00000442, &dmc0->directcmd);                   /* DLL Unreset */Writel (0x00010780, &dmc0->directcmd);                   /* OCD Default */Writel (0x00010400, &dmc0->directcmd);                  /* OCD Exit */Writel (0x0ff02030, &dmc0->concontrol);
        /* Auto Refresh on/* Writel (0XFFFF00FF, &dmc0->pwrdnconfig);

        Writel (0x00202400, &dmc0->memcontrol);
        /* DMC1 */Writel (0x00101000, &dmc1->phycontrol0);                 Writel (0x00101002, &dmc1->phycontrol0);
        /* DLL on */Writel (0x00000086, &dmc1->phycontrol1);                 Writel (0x00101003, &dmc1->phycontrol0);         /* DLL start */while ((Readl (&dmc1->phystatus) & 0x7)! = 0x7);

    /* Wait DLL locked */    Writel (0x0fff2350, &dmc1->concontrol);                  /* Auto Refresh Counter should be off */Writel (0x00202430, &dmc1->memcontrol);

        /* Dynamic power down should is off */Writel (0x40e01323, &AMP;DMC1-&GT;MEMCONFIG0);
        Writel (0xff000000, &dmc1->prechconfig);

        Writel (0XFFFF00FF, &dmc1->pwrdnconfig);                  Writel (0x00000618, &dmc1->timingaref);
        /* 7.8us * 200MHz = 1560 = 0x618 */Writel (0x19233309, &dmc1->timingrow);
        Writel (0x23240204, &dmc1->timingdata);

        Writel (0x09c80232, &dmc1->timingpower);                   Writel (0x07000000, &dmc1->directcmd);                   /* NOP */Writel (0x01000000, &dmc1->directcmd);                   /* PALL */Writel (0x00020000, &dmc1->directcmd);                   /* EMRS2 */Writel (0x00030000, &dmc1->directcmd); /* EMRS3 */writel (0x00010400, &dmc1->directcmd);                   /* EMRs Enable DLL */Writel (0x00000542, &dmc1->directcmd);                   /* DLL Reset */Writel (0x01000000, &dmc1->directcmd);                   /* PALL */Writel (0x05000000, &dmc1->directcmd);                   /* Auto Refresh */Writel (0x05000000, &dmc1->directcmd);                   /* Auto Refresh */Writel (0x00000442, &dmc1->directcmd);                   /* DLL Unreset */Writel (0x00010780, &dmc1->directcmd);                   /* OCD Default */Writel (0x00010400, &dmc1->directcmd);                  /* OCD Exit */Writel (0x0ff02030, &dmc1->concontrol);
        /* Auto Refresh on/* Writel (0XFFFF00FF, &dmc1->pwrdnconfig);
Writel (0x00202400, &dmc1->memcontrol); Third, initialize SD card copy function void Copy_bl2_to_ram (void) {/* * * CH: Channel * * SB: Starting block * * BS: Block size * * DST: Destination * I: initialInitialize */#iefine copysdmmctomem (CH, SB, BS, DST, i) \ (((unsigned char (*) (int, unsigned int, unsigned short, unsigned int*, unsigned char)) \ (* (((unsigned int *) 0xd0037f98))) (CH, SB, BS, DST, i)) unsigned int V210_sdmmc_bas  E = * (volatile unsigned int *) (0xd0037488);

        v210_sdmmc_base unsigned char ch = 0;
                /* Reference s5pv210 manual 7.9.1 sd/mmc REGISTER MAP */if (v210_sdmmc_base = = 0xeb000000)//Channel 0
        ch = 0;

        else if (v210_sdmmc_base = = 0xeb200000)//Channel 2 ch = 2;
COPYSDMMCTOMEM (CH, +, ten, (unsigned int *) config_sys_sdram_base, 0); The change base address is used for clock initialization and DDR initialization. The register address in H is struct s5pv210_clock *const clock = (struct S5pv210_clock *) Samsung_get_bas
E_clock (); Define this struct variable needs to be modified Cpu.h CD Arch/arm/mach-s5pv210/include/mach/vim cpu.h/* Add by Sourcelink */Is_samsung_type (s5pv210, 0x5 6210)/* Modif by Sourcelink */#define SAMSUNG_BASE (device, BASE) \ Static Inline unsigned int samsung_get_base_# #device (void) \ {\ if (cpu_is_s5pv210 ())                  \ return s5pv210_# #base;			\ else if (cpu_is_s5pc100 ()) \ return s5pc100_# #base; \} at first, the discovery execution is a register base address for s5pc100, and there is no reason to find it. The ID function of the s5pv210 is posted in the previous section. Want to know the friend told. The final change is as follows:/* MODIF by Sourcelink */#define SAMSUNG_BASE (device, BASE) \ Static inline Unsigne
                d int samsung_get_base_# #device (void) \ {\                          return s5pv210_# #base; \ */* Add by Sourcelink */samsung_base (dmc0,dmc0_base) samsung_base (dmc1,dmc1_base) Five, adding macros CONFIG_SPL compiling U-boot-spl.bin , Spl/makefile will export a macro config_spl_build, we use this macro to control whether the code is compiled, the following lists the modified framework #ifdef CONFIG_SPL_BUILD VI, hardware initialization CD board/samsung/ Smdkv210/vim Lowlevel_init. S/* Modif by Sourcelink */. Globl lowlevel_init Lowlevel_init:mov R9, LR #ifdef config_spl_BUILD BL clock_init/* Clock initialization */BL ddr_init/* DDR initialization */#endif mov pc, R9/* return */Seven, modify _main function CD Arch/arm/lib vim crt0.
 S ENTRY (_main)/* * Set up initial C runtime environment and call Board_init_f (0).     */* Modied by Sourcelink */#if!defined (config_spl_build) Ldr sp, = (CONFIG_SYS_INIT_SP_ADDR) bic SP, SP, #7/* 8-byte alignment for ABI compliance */Sub SP, SP, #GD_SIZE/* Allocate one GD AB Ove SP */Bic SP, SP, #7/* 8-byte alignment for ABI compliance */MOV R9, SP/* GD is above SP */mov r0, #0 #endif/* modied by Sourcelink */#ifdef config_spl_build BL COPY_BL 2_to_ram/* Copy BL2 to DDR */LDR PC, =config_sys_sdram_base/* Jump to DDR start address to execute BL2 */#els e bl board_init_f #endif viii. Modify the DDR base address vim include/configs/smdkv210.h/* DRAM base */#define Config_sys_sdra M_base 0x20000000/* modif by Sourcelink */* Text BASE */#define CONFIG_SYS_TEXT_BASE 0x20000 0009. Add the macro Vim Configs/smdkv210_defconfig # Add by Sourcelink Config_spl=y 10, adding an executable file that adds header information after nine steps have been done before compiling will prompt Mkexynosspl:co Mmand not find this is an executable file that is automatically added to the header information when make is analyzed scripts/makefile.spl vim SCRIPTS/MAKEFILE.SPL # Modif by Sourcelink $ (obj)/$ (B
        Oard)-spl.bin: $ (obj)/u-boot-spl.bin $ (if $ (wildcard $ (objtree)/spl/board/samsung/$ (board)/tools/mk$ (board) SPL), \ $ (objtree)/spl/board/samsung/$ (board)/tools/mk$ (board) spl,\ $ (objtree)/TOOLS/MKSOURCE210SPL) $ (VAR_SIZE_PA RAM) $< $@ endif make your own compiled executable Source210 change it to mksource210spl into the Tools directory 11, compile and write made Smdkv210_defconfig made spl/u-boot-  Spl.bin after compiling the smdkv210-spl.bin in the SPL directory to write to the SD card sector 1, and then burn to write another executable bin file to the SD card sector 32