Use Case Analysis of data cache in or1200

The following is an excerpt from the book "Step by Step surprise core-software core processor internal design analysis ".

 

13.7 one of the dcache usage scenarios-The dcache fails to target during Command Execution

The dcache loss target in the execution phase of storage commands has different execution processes under the write-through and write-back policies. The address corresponding to the memory is directly written under the write-through policy without the dcache operation. In the write-back policy, first determine whether the line of the Directory table in dcache corresponding to the target address is modified. If yes (dirty is 1), write the line back to the memory, then, read the memory block of the target address into dcache, fill in the corresponding line, and then modify the data of the corresponding Destination Address in dcache; if the line corresponding to the destination address is not modified (dirty is 0), read the memory block where the destination address is located into dcache and fill it with the corresponding line, then modify the data of the target address in dcache. 13.7.

 

(In the reference document of the specific analysis process)

13.8 dcache usage scenario 2-storage command execution stage dcache hit

The scenario of dcache hit in the execution stage of storage commands also has different execution processes under the write-through and write-back policies. Under the write-through policy, the line corresponding to the directory table in dcache must be written, also, write the address corresponding to the memory. Under the write-back policy, write the line corresponding to the directory table in dcache. 13.11.

(In the reference document of the specific analysis process)

 

13.9 dcache usage scenario 3 -- l. mtspr command write special registers in dcache

Dcache has three special registers: dcbir, dcbfr, and dcbwr, which are used in section 13.3. From code analysis, we can find that only dcbir and dcbfr can be used in the write-back policy, and all three special registers can be used in the write-back policy. This is also well understood. In the general writing policy, the line flag dirty in the dcache directory table is always 0, so dcbir and dcbfr play the same role, and there is no need to have the dcbwr register, therefore, in this chapter, the instruction L. mtspr write special registers in dcache can be divided into the following four scenarios:

(1) execute the command L. mtspr to write dcbir and dcbfr.

(2) execute the command L. mtspr to write dcbir under the write-back policy.

(3) In the write-back policy, run the command L. mtspr to write dcbwr.

(4) write the dcbfr command L. mtspr under the write-back policy

(In the reference document of the specific analysis process)

 

13.10 dcache analysis summary

Dcache has multiple usage scenarios. This chapter only analyzes three of them, but it is sufficient for us to understand the working process of dcache. The processing process of other scenarios is similar to this. I personally feel that the dcache module is the most complex module in or1200. Considering the loading and storage commands, the write policy should also be considered as write-through and write-back, it is complicated to consider the flag V and dirty of the corresponding directory items in dcache. Therefore, at the end of this chapter, the dcache workflow is shown in 13.18 and 13.19, respectively, in the case of write-through and write-back, the transition between States of the finite state machine in the dc_fsm module is also given.