Use wildcards in rules

Use wildcards in rules

If we want to define a series of similar files, we naturally think of using wildcards. Make supports three wildcards: "*", "?" And "[...]". This is the same as the Unix B-shell.

Tilde ("~") Characters are also used in file names. For example, /Test ", which indicates the test directory under the $ home directory of the current user. And "~ "Hchen/test" indicates the test directory under the user's home directory. (These are UNIX knowledge, make also supports) and in Windows or MS-DOS, the user does not have a home directory, the directory indicated by the Tilde depends on the environment variable "home.

Wildcards replace your series of files. For example, "*. c" indicates a file with a suffix of C. It should be noted that if our file name contains wildcards, such as "*", we can use the Escape Character "\", for example, "\ *" represents the true "*" character, rather than any string of length.

Well, let's take a look at several examples:

Clean:
Rm-f *. o

In the above example, I will not mention it much. This is a wildcard supported by the operating system shell. This is a wildcard in the command.

Print: *. c
LPR-p $?
Touch print

The preceding example shows that the wildcard can also be used in our Rules. The target print depends on all [. C] files. "$ ?" It is an automation variable. I will introduce it to you later.

Objects = *. o

The above example indicates that the token can also be used in variables. It does not mean that [*. O] will be opened, no! The value of objects is "*. O ". The variables in makefile are actually Macros in C/C ++. If you want to expand the wildcard in the variable, that is, to make the objects value a set of all [. O] file names, you can:

Objects: = $ (wildcard *. O)

This usage is pointed out by the keyword "wildcard". The keyword about makefile will be discussed later.