User-defined primitive udp_zt

User-defined primitive UDP
It enables the expansion of gate-level primitives to simulate 2 behaviors:
• Combinatorial behavior, simulated by a combination of UDP primitives;
• Timing behavior, which is simulated by the timing primitives of the UDP;
A UDP can have multiple inputs, but only one scalar output, the output can have 3 states: 0, 1, x, does not support high impedance Z, but the input Z-state is often used as the X-state.
1. Definition
The definition of UDP is independent of the module and belongs to the same level as the module.
Rules:
• Only one output port declaration is allowed and must be defined before the definition of the input port;
• There is no inout port and cannot be defined as a vector form;
• In timing UDP, the output port must be defined as a register type, while the output port in the combined UDP cannot be defined as a register type;
• The logical implementation body is all in the Status table table, each row has the same order of input excitation as the previous input port definition, regardless of what the port actually defines. Each input/output port in the table has a field, separated by a colon between the input and output fields, and each row defines the specific combination output produced by the input signal. In timing UDP, another domain is added between the input domain and the output domain, indicating the current state of UDP, which can be considered as the actual output of UDP at present. The output that is not listed for the input combination corresponds to X.
Format:
Primitive name (interface signal table);
Output

Port declaration;
Input
Table //Status table description;
Endtable
Endprimitive

UDP Status Table
Symbol

ExplainComments
0Logic 0
1Logic 1
XUnknown logic
?Logic 0, 1, or Xcannot be used for output
BLogic 0 or 1cannot be used for output
-No changeOnly for time series Primitives
(VW)From V to WCan it be 0, 1, x or?
* with (??) any changes in the input
R with () input rising Edge
F Same (ten) input falling Edge
P with (01), (0x), (x1) rising edge with X
N Same (10), (1x), (x0) falling edge with x

2. Combining UDP
example, define a combination of UDP and instantiate it,
Primitive mult (MUX,CONTROL,DATA1,DATA2);
Output MUX;
Input control,data1,data2;
Control Data1 Data2:mux
0 1 0:1;
0 1 1:1;
0 1 X:1;
0 0?: 0; 0, 1, x three cases to simplify the description table
1? 1:1;
1? 0:0;
x 0 0:0;
X 1 1:1;
Endtable
Endprimitive
The multi-channel selector is instantiated as follows,
Module EX1 (IN1,IN2,IN3,OUT1);
Input in1,in2,in3;
Output OUT1;
Wire OUT1;
Mult mult1 (out1,in1,in2,in3);
Endmodule

3. Timing UDP
There will be a storage element to store the current state. 2 types of power and edge sensitivity.
(1) Level-sensitive timing UDP: More than the combination of a register, mainly used to save the current state, can also be considered as the current output. The current input and status determine the next output, for example:
Primitive Udp_latch (Q1,DATA,CLK);
Output Q1;
Input DATA,CLK;
Reg Q1;
Initial
q1=0; Initialize output signal to 0
Table
Data clk:q1 (current) Q1 (next)
0 0:? : -;
0 1:? : 0;
1 0:? : -; Which means you don't care about the current state.
1 1:? : 1; It can be 0, 1, or X
Endtable
Endprimitive

(2) Edge-sensitive timing UDP: A change in the input trigger output, each row in the table can only have one input jump, D trigger for example:
Primitive D_edge (Q1,DATA,CLK);
Output Q1;
Input DATA,CLK;
Reg Q1;
Initial
q1=0;
Table
Data clk:q1 (current) Q1 (next)
0 (01):? : 0;//, rising edge
1 (01):? : 1;
No change in output values
0 (0x):? :-;//not selectable, no rising edge
1 (0x):? : -;
No change for Negedge
? (? 0):? :-;//not selectable, may be falling edge
No change for change in data
(??) ? : ? :-;//input changes do not affect the output
Endtable
Endprimitive

Example 2,t Trigger,
Primitive T_ff (q1,clk,clear);
Output Q1;
Input clk,clear;
Reg Q1;
Table
CLK CLEAR:Q1 (current) Q1 (next)
?

1:? : 0;
? (10):? :-;//ignores clear falling edge
(10) 0:1: 0;//Falling Edge Trigger flip
(10) 0:0: 1;
(0?) 0:? :-;//ignores rising edge of clock
Endtable
Endprimitive

To form a 4-bit loop counter:
Module Counter4 (q,clk,clear);
IO ports
Output [3:0] Q;
Input clk,clear;
T_ff tff0 (q[0],clk,clear);
T_ff tff1 (q[1],q[0],clear);
T_ff tff0 (q[2],q[1],clear);
T_ff tff0 (q[3],q[2],clear);
Endmodule

(3) Mixed timing UDP: Allows the simultaneous definition of the table in 2, when the input changes, the priority to handle the Edge trigger event, and then handle the level event; If an excitation triggers 2 events at the same time, the output is subject to the level event (which can be understood as the result of the later modification).
JK triggers describe mixed-timing UDP:
Primitive Jk_edge (q,clk,j,k,preset,clear);
Output q;
Input clk,j,k,preset,clear;
Reg Q;
Table
CLK J K Preset clear:q (state) Q (Output)
? ? ? 0 1:? : 1;//preset
? ? ? * 1:1: 1;
? ? ? 1 0:? : 0;//clear
? ? ? 1 *: 0:0;
R 0 0 0 0:0: 1;//normal clocking case
R 0 0 1 1:? : -;
R 0 1 1 1:? : 0;
R 1 0 1 1:? : 1;
R 1 1 1 1:0: 1;
R 1 1 1 1:1: 0;
F???? : ? : -;
b *??? : ? : -;
B? * ? ? : ? : -;
Endtable
Endprimitive

User-defined primitive udp_zt