Verilog blocking assignment and non-blocking assignment

1 Modulemain ();2 Regclk=0;3 Reg[ One:0] A=0;4 Reg[ One:0] B=0;5  always# -clk=~CLK;6  always@ (CLK)7 begin8a=a+4;9b<=a/4;Ten End One Endmodule

If you pour the two sentences in always, the output will change.

The above procedure 0~50s, b=1; change to the following situation after b=0;

1   Modulemain ();2   Regclk=0;3   Reg[ One:0] A=0;4   Reg[ One:0] B=0;5    always# -clk=~CLK;6    always@ (CLK)7   begin8b<=a/4;9a=a+4;Ten  End One  Endmodule

1) calculates the non-blocking assignment RHS expression at the beginning of the assignment time.
2) Update the non-blocking assignment LHS expression at the end of the assignment time.

keep these eight points in mind at the time of writing to the vast majority of Verilog users to solve the 90-100% risk competition problem in the integrated post-simulation.

1 "when the sequential circuit is modeled, it is assigned with a non-blocking value.
2 "When the latch circuit is modeled, it is assigned with a non-blocking value.
4) use non-blocking assignment when establishing timing and combinational logic circuits in the same always block.
6) do not assign a value to the same variable in more than one always block.
8) do not use #0 delay when assigning

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Verilog blocking assignment and non-blocking assignment