Verilog Case Coding Style

1, in general, the integrated device will Casestatements are synthesized into multi-channel selectors, but may also be integrated into priority decoders.

2, Case statement, if the conditions enumerated incomplete, will be integrated out of the unnecessary latch.

Integrated instruction://synopsys parallel_case &//synopsys full_case

Use the //synopsys parallel_case to guide the multiplexer to generate a multi-channel selector.

1  always@ (cs_state)2 begin3  Case(cs_state)//Synopsys Parallel_case4 2' B00:next_state =2' B01;5 2' B01:next_state =2' b00;6 2' B10:next_state =2' B10;7 default: Next_State =2' b00;8 Endcase9 End

Using //synopsys full_case avoids the need to generate unnecessary latches.

1  always@ (cs_state)2 begin3  Case(cs_state)//Synopsys Full_case4 2' B00:next_state =2' B01;5 2' B01:next_state =2' b00;6 2' B10:next_state =2' B10;7 Endcase8 End

Guideline1: using if-else-if encoding Priority codec / decoder,if-else-if The priority relationship is more clearly understood.

Guideline2: use case implementation to look up the table class statements, which can improve the readability of the code.

Guideline3: In General, do not use the "full_case parallel_case" directive in the Verilog case statement, It may cause inconsistencies in the behavior of the synthesis and emulator.

Guideline4:3 exceptions, you can use the "full_case parallel_case" directive to optimize the state machine encoding. The reason for this is simple, the unfinished condition, which is treated as don'T Care its assignment by

integrated automatic selection 0 or Span style= "font-family:mceinline;" >1 0 or 1

3.Avoid case statements generate unnecessary latch verilog recommended style: use default Statement assigns the default value (0 or 1), or the default value is assigned immediately after the statement , and case analysis is done for each condition .

4, case code example analysis.

EX1:

1 Modulemux3c (Y,a,b,c,sel);2 Outputy;3 input[1:0] sel;4 inputa,b,c;5 Regy;6 7  always@ (AorBorCorsel)8      Case(SEL)9         2'B00:y=a;Ten         2'b01:y=b; One         2'B10; Y=c; A         default: y=1'BX; -     Endcase - Endmodule 

The above code to the integrated device: When sel=11 ,y is don'T Care , and the integrated device uses the Carnot diagram simplification method for the logic optimization;

For the emulator: when sel=11 ,they value is x, unknown state. As a result, this also results in inconsistent behavior between the simulator and the emulator (the effect is the same as using full_case for the composite ).

EX2:

1 Modulemux3c (Y,a,b,c,sel);2 Outputy;3 input[1:0] sel;4 inputa,b,c;5 Regy;6 7  always@ (AorBorCorsel)8      Case(SEL)//Synopsys Full_case9         2'B00:y=a;Ten         2'b01:y=b; One         2'B10; Y=c; A      Endcase - Endmodule 

The above code is for thesel=11 , wheny is don'TCare, but the emulator will be a latch ( y values remain unchanged).

EX3: Default value (not x value) determined with default assignment

1 Modulemux3c (Y,a,b,c,sel);2 Outputy;3 input[1:0] sel;4 inputa,b,c;5 Regy;6 7  always@ (AorBorCorsel)8      Case(SEL)9         2'B00:y=a;Ten         2'b01:y=b; One         2'B10; Y=c; A         default: y=a;//or y=1 ' B0; -     Endcase - Endmodule 

Avoid the x value of the emulator by determining the value.

EX4: Assign default value immediately after entering Case statement

1 Modulemux3c (Y,a,b,c,sel);2 Outputy;3 input[1:0] sel;4 inputa,b,c;5 Regy;6 7  always@ (AorBorCorsel)8y=1'B0;9      Case(SEL)Ten         2'B00:y=a; One         2'b01:y=b; A         2'B10; Y=c; -     Endcase - Endmodule 

By first assigning a value, avoid forgetting to write the whole case condition and appear latch.

Verilog Case Coding Style