VGA Interface Design for ARM embedded platform

LCD is the choice for display terminals of most embedded products, but in some applications that require large screen display, industrial-level LCD is expensive and the existing Large Screen Display (including CRT Display and LCD display) generally, a uniform 15-pin VGA display interface is used. With its powerful functions and high cost-effectiveness, Samsung arm9-chip S3C2410 is widely used in embedded products. During the development of a blood rheological Tester Based on the ARM embedded platform, the author successfully used the high-performance video D/A conversion chip adv7120 to convert the LCD scanning interface of S3C2410 to the VGA interface, enable it to drive the VGA Interface display.

1 VGA Interface Introduction

In recent years, the industry has developed a number of digital display interface protocols, typically DVI (Digital Visual Interface ). Because the standards of digital interfaces have not yet been unified and vendors support their respective standards, the standards of digital interfaces have been delayed. VGA interface is a analog signal interface. As an interface standard in the display field for many years, it is still the most mature standard interface for all display terminals until now, some high-end TVs also support VGA interfaces.

The 15-pin VGA interface signal definition is shown in table 1. In addition to two NC signals, three display data buses, and five Gnd signals, three RGB color component signals and two scanning synchronization signals hsync and vsync are important signals. The color component in the VGA interface adopts the rs343 level standard. The standard peak-to-peak voltage of rs343 is 1 v. The four levels defined by this standard are:

White level -- + 0.714 V;

Black Level -- + 0.054 V;

Blanking level-0 V;

Synchronization level --- 0.286 v.

2 S3C2410 LCD controller Overview

Samsung's S3C2410 chip is powerful and cost-effective. It has been widely used in embedded products. The S3C2410 has an LCD controller that allows you to conveniently control the LCD display of the driving scanning interface.

2.1 pin function Information

The LCD Controller provides scanning data transmission pins and timing control pins, which are described as follows:

Frame synchronization signal between the vframe/VSYNC--LCD controller and the LCD driver. This signal tells the LCD screen that a new frame has started. The LCD controller inserts a vframe signal immediately after a frame is displayed to start displaying a new frame.

Synchronous pulse signal between the vline/HSYNC--LCD controller and the LCD driver. This signal is used by the LCD driver to transmit the content of the horizontal line shift register to the LCD screen for display. The LCD controller inserts a vline signal after the entire row of data is moved to the LCD driver.

Pixel clock signal between VCLK--LCD controller and LCD driver. The LCD controls to send data at the rising edge of the vclk, And the LCD Driver samples at the falling edge of the vclk.

AC signal for VM/VDEN--LCD drives. The VM signal is used by the LCD driver to change the voltage polarity of rows and columns to control the display of pixels. VM signals can be synchronized with each frame or vline signals of variable data.

VD [] -- LCD pixel data output port.

2.2 registers

The LCD control registers of S3C2410 mainly include: lcdcon1 registers, lcdcon2 registers, lcdcon3 registers, lcdcon4 registers, and lcdcon5 registers. The settings of these registers are closely related to display information, control timing, and data transmission formats, in the design, you need to correctly set these registers based on the specific information of the display device so that the S3C2410 can normally control and drive different display screens.

2.3 Internal Structure

The LCD controller of S3C2410 is used to transmit image data and generate corresponding control signals, including regbank (control register group), LCDCD-MA (dedicated DMA), vidpcs (Video Signal Processing Unit) and the time series signal generation unit (timegen), as shown in 1. Regbank contains 17 programmable registers and several 256 × 16 color palette memories, which are used to configure the LCD controller and set corresponding parameters. lcdcdma provides a fast transmission channel for video signals, the system bus automatically extracts video data from the system frame cache and transmits it to the video signal processing unit. After vidpcs shaping the signals extracted from the dedicated DMA and improving the driving capability, output to external data ports VD []; timegen and lpc3600 are responsible for generating the control sequence required by the LCD.

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3 VGA Interface Design

Use the high-performance video D/A conversion chip adv7120 to convert the LCD scanning interface that comes with s3c24l0 to the VGA interface, and then display it with a monitor with the VGA interface.

3.1 adv7120 Introduction

Adv7120 is a high-speed video digital-to-analog conversion chip produced by ADI. Its pixel scanning clock frequency is 30 MHz, 50 MHz, and 80 MHz. Adv7120 is integrated into three independent 8-bit high-speed D/A converters on a single chip, which can process the red, green, and blue video data respectively, it is particularly suitable for high-resolution analog interface display terminals and applications that require high-speed D/A conversion.

The input and control signals of adv7120 are very simple: Three 8-bit digital video data input terminals correspond to RGB video data respectively, and the data input end adopts the standard TTL level interface; the four video control signal lines include composite synchronous signal sync, blanking signal blank, white level reference signal ref white and pixel clock signal clock; an external 1.23 V digital-to-analog conversion reference voltage source and one output full adjustment. There are only four output signal lines: Analog RGB signals adopt high-impedance current source output mode, which can directly drive 75 Ω coaxial transmission lines; synchronous reference current output signal isync is used to encode Video Synchronization information in the green video analog signal.

3.2 schematic design

The synchronous signal of VGA interface is the same as that of LCD scanning interface. Using adv7120, you can easily convert the LCD scanning interface of s3c24l0 into a VGA interface, as shown in circuit principle 2.

The Synchronous scanning signals hsync and vsync In the S3C2410 processor interface are directly connected to the VGA interface. The vden signal (displaying valid data signals) is used to control the adv7120 chip. Because adv7120 requires a high accuracy for the reference level, it cannot be replaced by a resistive voltage circuit. The 1.2 V voltage reference chip ad589 is used to generate the reference voltage. In this circuit design, it should be noted that the analog and digital should be separated during PCB layout.

4. register settings for S3C2410

Taking the resolution 640 × 480, refresh frequency 60Hz, 16-bit color display mode as an example, according to the VGA interface synchronization signal sequence shown in figure 3, the lcdcon1 ~ The configuration of the lcdcon5 register.

4.1 lcdconl register

Linecnt: the Status bit of the row counter. Read-only, no need to set.

Clkval: determines the vclk frequency parameter. The formula is vclk = hclk/[(clkval + 1) × 2], in Hz. The hclk of the hardware system used by the author is 100 MHz. For a 640x480 display screen, vclk is required to be 20 MHz. Therefore, clkval must be set to 1.

Mmode: determines the VM change speed. Select mmode = O to change the mode of each frame.

Pnrmode: determines the scan mode. Select pnrmode = 0x3 as the tft LCD Panel scan mode.

Bppmode: determines the BPP (number of bits per pixel) mode. Select bppmode = 0xc as the TFT 16-Bit mode.

ENVID: data output and logic signal enable control bit. Select ENVID = 1 to allow data output and logical control.

4.2 lcdcon2 register

Vbpd: Determine the delay time before frame synchronization signal and frame data transmission. It is the ratio of the delay time before frame data transmission to the interval width of the row synchronization clock, vbpd = T3/T6 = 1.02 MS/31.77 μs = 32.

Lineval: determines the vertical direction of the display. Formula: lineval = YSIZE-1 = 479.

Vfpd: Determine the delay time of the synchronization signal to the next frame after the frame data transmission is completed. It is the ratio of the delay time after the frame data transmission to the interval width of the row synchronization clock, vfpd = T5/T6 = 0.35 MS/31.77 μs = 11.

Vspw: Determine the frame synchronization clock pulse width, which is the ratio of the frame synchronization signal clock width to the row synchronization clock interval width. 3, vspw = T2/T6 = 0.06 MS/31.77 μs = 2.

4.3 lcdcon3 register

Hbpd: determines the delay time before transmission of row synchronization signals and row data. It describes the number of vclk pulses in the delay time before transmission of row data, 3, vbpd = T7 x vclk = 1.89 μs x 25 MHz = 47.

Hozal: determines the horizontal direction of the display. Formula hozal = XSIZE-1 = 639.

Hfpd: determines the delay time for the synchronization signal to the next line after the row data transmission is completed. It describes the number of vclk pulses in the delay time after the row data transmission, 3, hfpd = T9 x vclk = 0.94 μs x 25 MHz = 24.

4.4 lcdcon4 registers

Hspw: Determine the pulse width of the row synchronization clock. Description of the number of vclk pulses in the row synchronous pulse width time, 3, hspw = 3.77 μs x 25 MHz = 94.

4.5 lcdcon5 registers

Vstatus: vertical. Read-only, no need to set.

Hstatus: horizontal. Read-only, no need to set.

Bpp24bl: confirm the display data storage format. Bpp24bl = 0x0 is set here for small-end mode storage.

Frm565: Determine the 16-bit data output format. Here, frm565 = 0x1 is set to output in the format.

Invvclk: determines the effective edge polarity of the vclk pulse. Based on the screen information, select invvclk = 0xl. When the vclk rising edge arrives, data transmission starts.

Invvllne: determines the polarity of the hsync pulse. As shown in figure 3, invvline = 0 X1 is selected as the negative pulse.

Invvframe: determines the polarity of the vsync pulse. As shown in figure 3, it is negative, so invvframe = 0x1 is set to select negative pulse.

Invvd: determines the pulse polarity of the data output. Based on the screen information, set invvd = 0x0 to select the positive pulse.

Invvden: determines the vden signal polarity. Based on the screen information, invvden = 0x0 is set as a positive polarity pulse.

Invpwren: determines the polarity of the pwren signal. According to the screen information, nvpwren = 0x0 is set as a positive polarity pulse.

Invlend: Determine the polarity of the Lend signal. Based on the screen information, invlend = 0x0 is set as a positive polarity pulse.

Pwren: The pwren signal output is allowed. Set pwren = 0xl to allow pwren output.

Enlend: The lend output signal is allowed. Set enlend = 0x1 to allow lend output.

Bswp: byte switch control bit. Set bswp = 0x0 to disable byte switching.

Hwswp: control bit for semi-word switching. Set hwswp = 0xl to enable semi-byte switching.

5. Discussion and summary

The S3C2410 processor can drive the VGA Interface in 24-bit color mode. However, when the data bus load of the processor is too high, the display effect is not ideal. The required data bandwidth is as follows:

The data bandwidth of the S3C2410 processor in 640x480X60Hz x 24-bit (resolution: 640x480, refresh frequency: 60Hz, 24-bit color) mode is: 640 × 480 × 60 × 4/(1 024 × 1 024) = 70.3 Mb/s (24-bit color actually occupies 32-bit data ), all the data must be obtained from the SDRAM through the system data bus in DMA mode. However, at a bus frequency of 100 MHz, the peak bandwidth of 32-Bit Memory is 100 × 32/8 = 400 Mb/s, and the actual bandwidth is 100 ~ 200 Mb/s. Therefore, the display data of 70.3 Mb/s is too heavy for the S3C2410 processor, and the screen of the monitor often appears a short black screen. This is because the system bus is too busy and the data on the LCD scanning interface cannot keep up. The scanning clock frequency temporarily slows down, causing the synchronization signal of the CRT display to be invalid. If the 16-bit color mode is used, the data bandwidth is reduced to 640x480X60x2/(1 024x1 024) = 35.2 Mb/s. In actual testing, the VGA image of 640x480 is displayed normally in 16-bit color mode at 60Hz.

In summary, if you want to support high resolution and high update rate display, you need a relatively large data bandwidth, which requires a high processor frequency and bus frequency. The current embedded processor has great limitations in these aspects, but this design can fully support the CRT display in 16-bit color 640 × 480 × 60Hz display mode, if the LCD is used as the display interface, the LCD has different requirements on the fl rate than the CRT display, and the LCD can be normally displayed when the fl rate is 30Hz. This design has great practical value and reference significance for solving the problems of Large Screen Display in ARM-based embedded systems.