What is OHCI, uhci, and EHCI?

OHCI, uhci and EHCI are USB spec compatible and provide an interface to different hardware host controller implementations. Multiple implementations of hardware host controllers allow for evolution and creativity within the USB spec.

In order to achieve the unification of USB Host functions and improve system reliability and portability, the upstream chip manufacturers have also determined the corresponding host specifications while determining the USB standard. Currently, there are three widely used EHCI (enhanced Host Control Interface) specifications. The same is Intel's uhci (Universal Host Control Interface host) and the OHCI (Open Host Control Interface open Host Control Interface) released by Compaq and Microsoft) it can be used in full speed and low speed USB systems. The hardware requirements and system performance, software complexity requirements are relatively low, but also can meet the requirements of most embedded systems with USB interfaces. In the comparison between uhci and OHCI, uhci has fewer hardware requirements, however, the processing capability and software development requirements for the system are relatively high (uhci is widely used in PCs); OHCI defines more functions in hardware, the content to be processed by the software is relatively easy, and the requirements for system processing capabilities and system resources are low. Therefore, in the embedded USB Host function, hardware that complies with OHCI specifications is selected, which simplifies the system design.

Master Controller

The main controller (HC) controls the transmission of packets on the bus. Frame in 1 ms. At the beginning of each frame, the master controller generates a frame start (SOF, start of frame) package.

The sof package is used to synchronize the start and the number of frames to be tracked. Packets are transmitted in frames, from the host to the device (out), or from the device to the host (in ). Transmission is always initiated by the host (polling transmission ). Therefore, each USB bus can have only one host. Each packet has a status phase during transmission. The data receiver can return ack (Response receipt), Nak (retry), and stall (error condition) or nothing (chaotic data stage, device unavailable or disconnected ). Section 8.5 of the USB specification details the package. Four different types of transmission can appear on the USB Bus: control, bulk, interrupt, and isochronous ). The transmission types and their features are described below (in the 'pipeline 'subsection ).

Large transmission between devices and device drivers on the USB Bus is divided into multiple packages by the master controller or HC driver.

Device Requests to the default endpoint (control transmission) are somewhat special. They consist of two or three phases: setup, data (optional), and status ). Set-up (set-up) packets are sent to the device. If there is a data phase, the direction of the data packet is given in the Set package. The direction in the status phase is the opposite to that in the data phase, or in when there is no data phase. The master controller hardware also provides registers to save the current status of the root port and the changes that have occurred since the last reset of the status change register. USB specification [2] A virtual hub is recommended for access to these registers. The virtual hub must comply with the hub device category described in Chapter 11th. It must provide a default pipeline so that device requests can be sent to it. It returns a specific set of descriptors of the standard and hub classes. It should also provide an interrupt pipeline to report changes to its ports. Currently, two available master control specifications are available: universal Master Control Interface (uhci; Intel) and open Master Control Interface (OHCI; Compaq, Microsoft, and National Semiconductor ). Uhci specifications are designed to reduce hardware complexity by requiring the master controller driver to provide complete scheduling for each frame of transmission. The OHCI Controller provides a more abstract interface to complete a lot of work and thus is more independent.

13.2.1 uhci
The uhci master controller maintains a list of 1024 frames pointing to the data structure of each frame. It understands two different data types: Transport Descriptor (TD) and queue header (QH ). Each TD represents a packet that communicates with the device endpoint. Qh is a way to divide some TD (and QH) into groups.

Each transmission is composed of one or more packages. The uhci driver divides large transmissions into multiple packages. In addition to synchronous transmission, a QH is allocated for each transmission. For each type of transmission, there is a QH corresponding to this type, and all these QH will be concentrated on this Qh. Due to the fixed latency requirement, synchronous transmission must be executed first. It is directly referenced by a pointer in the frame list. The last synchronization TD transmission references the QH of the interrupted transmission of that frame. All QH of the interrupted transmission points to the QH of the control transmission, and the QH of the control transmission points to the QH of the large transmission. The following chart provides a graphical overview:

This causes the following scheduling to run in each frame. After the Controller obtains the pointer of the current frame from the frame list, it first executes TD for all the synchronous (isochronous) packets in that frame. The last of these TD s references the QH of the interrupted transmission of that frame. The master controller then goes down from the qh to the qh of each interrupted transmission. After that queue is completed, the QH that interrupts transmission directs the Controller to all QH that control transmission. It will execute all the sub-queues waiting for scheduling there, and then all the transmissions queuing in the large Qh. To facilitate the processing of completed or failed transfers, the hardware will produce different types of interruptions at the end of each frame. In the last Td of the transfer, the HC driver sets the interrupt-on-completion bit to mark an interruption when the transfer is complete. If TD reaches its maximum number of errors, an error is marked as interrupted. If the short packet detection bit is set in TD and the packet length is smaller than the configured packet length, the interrupt is marked to notify the controller driver that the transfer is complete. Find out which transmission is completed or the task that generates an error is the master controller driver. When an interrupted service routine is called, it locates all completed transmissions and calls their callbacks.

For more detailed descriptions, see uhci specification.

 

13.2.2 OHCI

It is much easier to program the OHCI master controller. The Controller assumes that a group of endpoints are available and knows the scheduling priority and sorting of different transmission types in frames. The main data structure used by the master controller is the endpoint Descriptor (ed), which is connected to a queue of transport Descriptor (TD. Ed contains the maximum package size allowed by the endpoint, and the Controller Hardware completes package segmentation. After each transmission, the pointer pointing to the data buffer is updated. When the start and end pointers are equal, TD will return to the Completion queue (done-queue ). The four types of endpoints have their own queues. The control and bulk endpoints are queued in their own queues. The interrupted ed queues in the tree, and the depth of the tree defines their operation frequency.

Frame list interrupt synchronization (isochronous) control bulk)

The scheduling of the master controller running in each frame looks as follows. The Controller first runs non-periodic control and bulk queue, which can be up to a time limit set by the HC driver. Then, use the lower five digits of the frame number as the index in the layer where the depth of the Ed tree is 0 to run the interrupted transmission of the frame number. At the end of the tree, the synchronous Ed is connected and then traversed. Synchronization TD contains the frame number of the first frame in which the transmission should run. After all the periodic transmissions have been run, the control and bulk queues are traversed again. Interrupt service routines are periodically called to process completed queues, call callbacks for each transmission, and reschedule interrupt and synchronization endpoints.

For more detailed descriptions, see OHCI specification. The service layer, that is, the middle layer, provides controllable access to devices and maintains resources used by different drivers and service layers. This layer handles the following aspects:

Device Configuration Information

Pipeline for communication with devices

Detects and connects devices, and detach devices from devices ).

Article Source: http://www.diybl.com/course/6_system/linux/Linuxjs/200883/134587.html