What is write-allocate policy?

in aCachesingle-machine system, there are usually two write strategies:Write throughand theWrite back. Both of these write strategies are for write hits (Write Hit) In the case of:Write throughis both writtenCachealso writeMain Memory;Write backis only writtenCache, and useDirtyflag bit recordCachemodification until the modifiedCachewhen the block is replaced, the modified content is written backMain Memory. Then the write fails (Write Miss), that is, the address you want to write is notCache, what should I do? One way is to write the content directly backMain Memory, this approach is calledNo write allocate policy, the other way is to write the address of the block first fromMain MemoryTransfer inCachein, and then writeCache, this approach is calledWrite allocate policy.

in aCacheMulti-processor system, there will still be write failures (Write Miss) situation, andNo write allocate policyand theWrite allocate policycan still be used. What needs to be discussed is just the appearanceWrite Missafter this situation,Snooping Cachewhat to do with the problem. Assuming that the write operation is performedP1, the listener isP2of theCache, then no matterP1when you perform a write operation, it isWrite Hitor isWrite Miss,P2of theCache(i.e.Snooping Cache) will checkP1is the address written inP2of theCacheif the execution isWrite Invalidpolicy, thenSnooping Cacheor place the corresponding blockInvalid, or do nothing (because it does not have a corresponding block), will certainly not put the other processor to write the block into its ownCache(because it doesn't make any sense).

through such analysis, we can think that the English original book p597 the first sentence of the second paragraph: "Another variant is loading the snooping cache on write misses" The meaning of the expression is inaccurate, and only once in the whole second paragraph. Snooping Cache , the rest of the place was never mentioned. So, I think the exact expression should be:"Another variant is loading the cache on write misses".

The above is to turn a teacher. If you want to look at the picture, the comparison image in this wiki.

Http://en.wikipedia.org/wiki/Cache_ (computing)

The ARM manual is actually very thin, but it takes more patience to look at it.

Http://infocenter.arm.com/help/topic/com.arm.doc.ddi0488c/DDI0488C_cortex_a57_mpcore_r1p0_trm.pdf

Write-back read-write-allocate

This was expected to being the most common and highest performance memory type. Any read or

Write to this memory type searches the cache to determine if the line is resident. If It is, the line

is read or updated. A store that hits a write-back cache line does not update main memory.

If the required cache line was not in the cache, one or more caches lines is requested from the L2

Cache. The L2 cache can obtain the lines from it cache, from another coherent L1 cache, or

From memory. The placed in the L1 cache, and the operation completes from the L1

Cache.

Write-back no-allocate

Use Write-back no-allocate memory to access data, might is in the the cache because other

Virtual pages that is mapped to the same physical Address is Write-back

Read-write-allocate. Write-back no-allocate memory avoids polluting the caches when

Accessing large memory structures that is used only one time. The cache is searched and the

Correct data is delivered or updated if the data resides in one of the caches. However, if the

Request misses the L1 or L2 cache, the line was not allocated to that cache. For a read that misses

All caches, the required data was read to satisfy the memory request, but the line was not added to

The cache. For a write this misses in all caches, the modified bytes is updated in memory.

Note

The NO-ALLOCATE allocation hint is only a performance hint. The processor might in some cases,

Allocate Write-back No-allocat

6.4.4 non-cacheable Streaming Enhancement

Can enable the cpuactlr[24], non-cacheable streaming enhancement bit, only if your

Memory system meets the requirement that caches line fill requests from the multiprocessor is

Atomic. Specifically, if the multiprocessor requests a cache line fill on the AXI master read

Address channel, any given write request from a different master is ordered completely before

or after the cache line fill read. This means, the memory read for the cache line fill

Starts, writes from any and master to the same cache line is stalled until that memory read

Completes. Setting This bit enables higher performance for applications with streaming reads

From memory types that does not allocate into the cache.

Because It is possible to build a AXI interconnect that does not comply (VI. Compliance, obedience, compliance, promise) with the specified< /c1>

Requirement, the cpuactlr[24] bit defaults to disabled.

Memory operations from bus to bus can be done with cache line only. Is this DMA?

6.4.7 Preload instruction Behavior

The multiprocessor supports the PLD, PLDW, and PRFM prefetch hint instructions. For Normal

Write-back cacheable memory page, the PLD, PLDW, and PRFM L1 instructions cause the line to be

Allocated to the L1 data cache of the executing processor. The PLD instruction brings the line into

The cache in Exclusive or Shared State and the PLDW instruction brings the line into the cache in

Exclusive State. The preload instruction cache, Pldi, is treated as a NOP. PLD and PLDW Instructions

Is Performance hints instructions (? Only and might is dropped in some cases.

Performance hints instructions how to understand? Because hint is the meaning of hints and hints.

This is understood first as "instructions for inferring/implying performance"

What is write-allocate policy?