Writing the operating system by yourself-Reading Notes-first recognized protection mode

Chapter 3 section 1 is "Awareness protection model", preliminary
This section describes the Global Descriptor Table gdt, segment descriptor, segment Selection Sub-table in protection mode, and entry into protection mode from real mode. When I read this last year, if I did not take notes when I used to study the protection mode
It is hard to understand, because the materials provided by the author are not systematic enough. It is not easy for people who have learned only 8086 assembler languages. The following content is generally based on my previous notes.
Point. (You can also refer to the information collected in the previous protection mode. Unfortunately, the mobile hard disk is broken and no information is available. You should have paid attention to information security for a long time .)

• Descriptor and Descriptor Table
  

8086 is a 16-bit processor with 16-bit registers and data bus and 20-bit address bus with addressing capability of 1 MB. The address consists of the base address and offset. Both the base address and offset address are 16
The physical address is calculated as follows: physical address = Segment Base Address × 16 + segment offset. Since 80386, the intel processor has entered the 32-bit era. The address bus is 32-bit, and the addressing capability is
4 GB. At this time, the general register is changed from 16 bits to 32 bits, but the segment register is still 16 bits. The original base address and offset value physical address calculation method is no longer applicable, new compute
Method.

When more than 386 of the CPU runs in the protection mode, although the segment register is still 16 bits, its meaning has changed: it no longer indicates the segment base address, it indicates the index of the segment descriptor in the descriptor table. In this case, the segment register value also has a new name: Segment Selection Sub.

Segment descriptor

Yes
An 8-byte data structure of the description segment attribute, which can be divided into three types: (Data Segment and code segment) segment descriptor, system segment descriptor, and gate descriptor. The structure of the descriptor is displayed on page 1 of the book. The book says, "Because
Historical problems. They (the base address and offset of segments in the descriptor) are all separated and stored ". I think this historical problem refers to the design compatible with the 80286 processor: 80286 uses a 24-bit address line, addressing
The capacity is 16 MB, so the segment base address is split into two parts: Low 24-bit and high 8-bit. 80286 has introduced the concept of "protection mode", which is the watershed for introducing the real mode and protection mode CPU. Two rough introductions
Shao 80286 Web site: http://wiki.ccw.com.cn/80286
Http://baike.baidu.com/view/193778.htm

Descriptor Table
Is the region where one or more descriptors are stored in the memory, and the start address is indicated by the relevant registers (GDTR, ldtr, idtr. There are three descriptor tables:

Gdt global description table Global Descriptor Table

LDT local description table Local Descriptor Table

IDT interrupt description table Interrupt Descriptor Table

Segment Selection Sub-
Yes
Segment register content. Although the 386 processor's mid-range register is still 16-bit, in the protection mode, the meaning of its content has changed. It does not represent the segment base address, but the segment descriptor in the description
Position in the table. Among them, the 0th and 1st bits are RPL (request privilege level
Request privilege level), used for access permission check, this will be described in detail later; 2nd bit is Ti (Task
Indication, task indication). If the value is 0, gdt is used. If the value is 1, LDT is used. If the value is 3rd to 15, segment descriptors are indexed in the corresponding Descriptor Table.

• Memory addressing
  
  

The addressing mode in real mode is the same as that in 8086: Segment Base Address × 16 + segment offset address.

In protection mode, use the 48-bit address pointer: The 16-bit segment selector and the 32-bit segment offset address. The addressing process is as follows: extract the segment from the corresponding segment register and select the child, and obtain the segment from the corresponding Descriptor Table based on the 13-bit high.
Descriptor: uses the 32-bit base address given by the segment descriptor and the 32-bit offset address to obtain the 32-bit linear address. If paging is not enabled, the 32-bit linear address is the physical address, otherwise, the linear address goes through
The paging mechanism is converted into a physical address. Of course, the addressing process performs various checks based on the segment attribute given by the segment descriptor, such as the privileged level check, the address out-of-bounds check, and whether the segment page exists.

• Register Model
  
  

In my opinion, failing to provide a Register Model of 386 is a major defect in this book. The Register Model of 386 is provided and briefly described here. (It took me a long time to use Wps office to draw this image)

The Shadow part in the figure is a register available in real mode.

General registers in eax, EBX, ECx, and EDX: 8086 have been extended to 32-bit. Of course, you can still use ax, BX, CX, dx to access 16 low bits; or use ah, Al and so on to access two low 16 bits.

CS, DS, SS, es, FS, and GS: Two 16-bit segment registers, FS and GS, are added. The usage of CS, DS, SS, and es remains unchanged. It is also a code segment, data segment, stack segment, and extended segment register. FS and GS can also be seen as extended segment registers for programmers.

EIP: The address is changed to 32 bits, and the Instruction Pointer must be expanded to 32 bits.

ESP, EBP, ESI, EDI: Stack pointer, base address pointer, source address change, target address change register. The name is extended to 32 bits with the letter E in front of it.

Eflags: the flag register is also 32-bit.

The following are new registers in 386:

Idtr, GDTR, and ldtr: idtr and GDTR are 48-bit, respectively used to save the base address (32-bit) and limit (16-bit) of the Interrupt Descriptor Table and Global Descriptor Table ). Ldtr Protection
Select Sub-segments for storing local descriptors. The usage is as follows: 1. Select Sub-segments for ldtr installation. The CPU automatically extracts local descriptors from gdt and stores them in the cache, create a LDT for the current task; 2
When we use the segment register selection in the future, if the Ti bit is found to be 1, we will find the corresponding segment descriptor from the LDT for addressing.

TR: The task register. It is used to store the task status segment and select a child to indicate the position of the task status segment descriptor in gdt (similar to ldtr ). Usage is similar to ldtr: In TR, select Sub-, CPU
Automatically retrieves the task status segment descriptor from gdt and puts it into the cache to create a TSS for the current task. Tss is the task state.
Short for a segment (Task status segment), which defines the information required to start a task. In short, it is (inaccurate) information about a process.

Cr0, CR1, CR2, Cr 3, and Cr4: control registers, which store various flag spaces of the system. Among them, the low 16 bits of Cr0 are MSW (Machine
State word, machine status word ). Here, we need to pay attention to the 0th-bit PE mark of Cr0. The value 0 indicates that the current operation is in real mode; the value 1 indicates that the current operation is in protection mode.

• Enter protection mode

The book provides the code for entering the protection mode. For more information, I will not give my own code. I will briefly describe the code in one place: why define an unused null descriptor at the starting position of gdt?
I haven't figured out this question for a long time, but I found the answer on the Internet: the descriptor with the index 0 in gdt is a special null Descriptor and cannot be used, if you use it for memory access, a Genernal protection exception is thrown. For this question, you can refer to the http://leonstar.bokee.com/36918.html