Xilinx FPGA Learning Note 1: Resources

in the Xilinx's FPGA , clock network resources are divided into three categories: Global clock resources and Zone Clock resource .

the global Clock resource is a dedicated interconnect network that reduces clock skew, duty-ratio distortion, and power consumption to increase jitter tolerance. Xilinx's global clock resources have designed dedicated clock buffers and drive structures to minimize the delay of global clocks reaching CLB, IOB, and Bram.

The Zone Clock Resource is independent of the global Clock network. Xilinx's devices are divided into a number of clock regions , taking Virtex-6 as an example, the smallest partof the Virtex-6 has 6 regions and the largest device has 18 regions. Unlike the global clock, the zone clock signal X can only drive a defined clock region .

This refers to the concept of a regional clock, which needs to be explained. Xilinx's FPGA devices manage clock networks through the clock area, with Virtex-6 as an example, with a fixed clock area of 40 CLB high and a half wafer width. Therefore, large-size devices have more clock areas. As shown, the FPGA devices in a total of 6 clock area, three on the left side three, from the figure can be seen in the height of each area is 2*20clbs, the area width is half the width of the FPGA chip. The middle is the CMT Clock Management module.

In the middle direction of each clock area there is a clock line (Hrow), take Virtex-6 as an example, a clock line, a total of 12 horizontal clock lines , 12 horizontal clock lines can all be driven by the global clock BUFG. It can also be driven by clock component buffers within the zone, such as BUFH and BUFR. This time someone will ask what is BUFG, Bufr and BUFH.

First to explain the BUFG, this is relatively simple, is the global clock network clock driver, if the clock signal to go global clock network, must be driven by this BUFG, BUFG can drive all clb,ram,iob. Spartan6 has a total of 16 BUFG global Clock lines . The vertex-6 has a total of 32 BUFG global Clock lines . See below for reference links.

Looking at the horizontal global clock tree in the BUFH,BUFH Drive area, Xilinx clocks are distributed through the clock tree, taking the spartan6 clock tree as an example. The FPGA intermediate vertical row is the CMT Clock Management module, which is the PLL and DCM. The global clock buffer BUFG is located at the center of the FPGA device, and the input of the clock can come from the upper, lower, left, and right bank of the FPGA, or from the PLL or dcm;16 bufgmux by driving vertical spine and vertical Spine to the north-south direction,vertical spine is equivalent to the trunk of the clock tree , according to this line, the clock level extends to the HCLK clock column and the HCLK clock column provides access to the local logical primitive path, HCLK and the so-called horizontal clock line, the equivalent of a branch ; each of the HCLK columns has 16 horizontal clock buffers on each side of the BUFH to drive the left and right logical resources.

To Vertex-6 each of the HCLK columns on each side have 12 horizontal clock buffer bufh drive the left and right logical resources, that is, each clock region has 12 bufh clock line . Such as

finally explained Bufr,bufr I did not see in the SPARTAN6 Clock Resource manual UG382, should be not ah. The BUFR is an area clock buffer that must be instantiated BUFR to enter the regional clock network. A BUFR can drive an area clock in up to three adjacent clock regions. The BUFR in the top and bottom areas can only connect to one of the adjacent clock regions, that is, the top BUFR connects to the next adjacent area where it resides. The BUFR at the bottom can only connect to an adjacent area on top of it. Therefore, the bottom and top bufr are scoped to two clock regions. For example, there is a total of 8 clock regions of the FPGA, each clock region contains up to 6 bufr clock lines . As of now you can see (purple callout) Each clock area of the vertex device, a total of 6 bufr and 12 bufh. SPARTAN6 each clock area seems to have 16 bufh. Finally, the BUFR can not only drive Io, but also drive clb,ram. The BUFIO received below can only drive the IOB module. BUFR can also 1-2-4-8 the crossover.

Finally, say it. Bufio,bufio is used to drive the I/O column of the dedicated clock network, the dedicated clock network independent of the global clock resources, suitable for the acquisition of source synchronization data. Bufio can only be driven by clock-capable I/O located in the same 1: zone. A clock area has 4 Bufio, 2 of which can drive an I/O clock network for adjacent areas. Bufio cannot drive logical resources (CLB, Bram, and so on) because I/O clock networks exist only in I/O columns.

Specifically these clock components buf how to use, I have not practice, first of these buf concept understanding, for your reference only. Younger brother Beginner, certainly has the understanding wrong place, everybody please correct me.

Links to reference documents:

http://xilinx.eetrend.com/blog/1957

Http://blog.sina.com.cn/s/blog_bff0927b010173bp.html

http://www.tools138.com/front/article/queryById.htm?id=417885

Xilinx FPGA Learning Note 1: Resources