Xilinx Vivado Usage Details (5): Call the user-defined IP core of the encapsulated

Zedboard OLED Display Controller IP v1

Introduction

Author:zhangxianhe

This document provides instructions for quickly adding, connecting, and using the Zedboardoled v1.0 IP core. Test applications running on ARM processor systems are used to communicate with IP through the capabilities of their drivers. The Vivado design suite is used as a development environment. Hardware validation is done on Zedboard, however, this IP can be easily applied to other motherboards or embedded systems.

Platform

Hardware: Zedboard xc7z020clg484-1

Software: Vivado 2016.3 (for Vivado 2015.4 and above)

Process

A-creating a project in Vivado to target the Zedboard

1. Double-click Vivado2016.3 to start Vivado;

2. Double-click Create New project to create a new project, click Next;

3. In the next window enter "Test_oled" as the project name, the project file is designated to be stored in the "d:/oled_test" directory, tick Create Project subdirectory, click Next;

4. Next, specify the project type, use the default selected RTL project, and tick do not specify sources at this time. RTL stands for Register delivery language (register Transfer Language), by selecting this option, we can add/modify the source file flexibly in the future, click Next;

5. Next, specify the board to test the project on, select Zedboard Zynq Evaluation and Development Kit, click Next and Finish;

The New Project Wizard closes and the project you just created opens in Vivado.

B-creating the ARM processor system using the IP integrator.

1. Click Create Block Design in Project manager at the top left of Vivado;

2. Enter the name of the module and click OK, for this example, use the name: System;

3. After clicking OK, a blank block Diagram view graphical user interface will be displayed in Vivado. In the diagram, we will add the required hardware block system.

4. Now we will add the ZYNQ7 processing system block that contains the ARM processor by starting the Add IP Wizard, or you can right-click the Add Ip..,ip directory window in the blank space of the program diagram to display the add all possible IPs in this design;

Scroll down to the bottom or use the keyword ZYNQ to search, double-click ZYNQ7 processing System. The ZYNQ7 processing system block has been placed in the Block Diagram view. The ports shown in the block diagram are defined by the default settings for the blocks specified by the target Development Board. Click Run Block Automation in the green Information Bar. Confirm Processing_system7_0 and make sure that apply Board Preset is selected, and then click OK.

This creates an external port for the processing system and applies physical constraints to those ports, as shown in

c-adding the zedboardoled IP to the IP repository

In the Process Navigation Pane, click the Project setting option, select IP, and then click the Add Repository button. Open the Browse window, browse to the location of the IP core (D:\oled_test\tamu.edu_user_ZedboardOLED_1.0), and click Select.

Notice how the tool detects a new IP in the directory, click Apply, and then OK.

When you do this, you can add zedboardoled_v1.0 to the IP library of the current project, and the next step is to add it to the block design and connect it from one side to the Zynq processing system, and connect to the OLED plate from the other side by using an external port.

D-connecting the zedboardoled IP core

1. Right-click in the program block diagram to select Add IP. Then enter "OLED", zedboardoled_v1.0 will be displayed, double-click on IP to add it to the block design.

2. See designer assistance can now be found in the green InfoBar, which will help connect the IP core to the AXI subsystem of the processing system, configure the clock and reset, assign a base address (0x43c00000) to the IP, and add the necessary hardware for interconnection and synchronization;

Click Run Connection Automation and select/zedboardoled_0/s00_axi. Keep the clock connection set to Auto, and then click OK. (default selection).

Click (Regenerate layout) to regenerate the layout, and the program block diagram should look similar to this:

Note that designer assistance automatically adds Axi interconnect and processor System reset. Hover over the zedboardoled Sdin port until it becomes a pencil shape, Then right-click and select Make External. (SCLK,DC,RES,VBAT,VDD) Ports repeat the same process.

3. Right-click anywhere on the program diagram and choose regenerate layout (regenerate layouts), which neatly organizes the blocks in your design.

The final layout looks similar to the following:

Click Tools, select Click Validate Design, check the program block diagram for errors, and click OK directly.

4. In the source pane, select the system diagram "system.bd", right-click and select Generate Output products, default settings, direct point generate, after the run is finished, click OK.

In the source pane, select the system block Diagram "system.bd", right-click and select Create HDL Wrapper, select the second let Vivado manage Wrapper and auto-update, click OK,

Now we connect IP to the processing system via the Axi interface, and the next step is to connect the external port of the IP core to the actual ZYNQ pin of the OLED module.

5. In the Flow Navigator window, select Add Sources from the Project manager section. The Add Sources dialog box opens. Select Add or Create Constraints. For pin constraints.

Click Next, and then click Create File, select XDC as the document type and enter Oled_constraints as the file name.

Click OK, click Finish to create the file and close the dialog box.

In the Sources window, expand the Constraints folder and open the newly created Xdc file by double-clicking Oled_constraints.xdc.

Add the following lines to the constraint file, or you can copy their package oled_constraints.xdc from the source file.

1 set_property package_pin U10 [get_ports DC]2 set_property package_pin U9 [get_ports RES]3 set_property package_pin AB12 [get_ports SCLK]4 set_property package_pin AA12 [get_ports Sdin]5 set_property package_pin U11 [get_ports VBAT]6 set_property package_pin U12 [get_ports VDD]7 set_property iostandard LVCMOS33 [get_ports DC]8 set_property iostandard LVCMOS33 [get_ports RES]9 set_property iostandard LVCMOS33 [get_ports SCLK]Ten set_property iostandard LVCMOS33 [get_ports Sdin] One set_property iostandard LVCMOS33 [get_ports VBAT] ASet_property Iostandard LVCMOS33 [Get_ports VDD]

This connects the external port of the zedboardoled IP core to the specific pin of the ZYNQ device. A specific pin is connected to the OLED module on the Zedboard. Press (Ctrl + S) to save the constraint file.

E-generating bitstream

In the Program and Debug section of the Flow Navigator window, click Generate Bitstream, a dialog box appears asking you to save your changes, click Save, or you may see a dialog box that says "No Implementation Result Available ", click Yes to run the synthesis and implementation. Generating a bitstream may perform the entire implementation process after synthesis, click Yes to run the implementation when prompted. The implementation may take some time to complete, depending on the performance of the computer.

The process of performing generate bitstream is performed automatically when the analysis is integrated and implemented. (This can also be done directly by clicking Run synthesis and then clicking Run implementation to implement it, and then clicking Generate Bitstream Generating the bitstream). When you are done, you can click Cancel directly.

F-exporting Hardware design to SDK

1. Click File > Export > Export Hardware to make sure the Include bitstream option is checked

2. Select the File>launch SDK, open the SDK, and note that all design-related files (including IP) have been exported to the SDK in the previous step, and the exported resources include drivers for the ZEDBOARDOLED_V1_0 IP core.

G-working with SDK

1. In the SDK, select File > New > Application Project.

2. In the next window, enter the file name and the default parameters as follows:

Click Next, in the next window, select Empty application from the available templates and click Finish. This will compile the BSD and related drivers.

3. Expand Oled_test_bsp>ps7_cortexa9_v2_0>libsrc>zedboardoled_v1_0>src, Then check the ZEDBOARDOLED.C and ZedboardOLED.h to implement features that work with the OLED screen.

4. Now we will write a simple application that uses these functions, extend the Oled_test directory, right-click the src directory, select new-> source file, display it in the next window, enter "MIAN.C" in the source file, and click Finish.

Copy and paste the following C code into "MAIN.C", click Save or tap (Ctrl + S) so that the Oled_test application and its BSP will be automatically compiled to generate the executable. elf file.

1 intMainvoid){2 Clear ();3Print_message ("Oled_test_zhang",0);4Print_message ("njupt__xian_he_",1);5Print_message ("ps_and_arm_pl_s",2);6Print_message ("Anniversary1229",3);7 return(1);8}

Cick project-> Clean (in case you get any errors with the BSD).

H-downloading the bitstream and running the application (Hardware verifications)

Hardware preparation: Two USB cable, one connection Micro-usb cable between the PC and the PROG port of the board; the other MICRO-USB cable between the PC and the UART Port of the board,. Turn on the power of the Zedboard board, power on after powering on;

1. Select the Xilinx tools-> program FPGA to download bitstream (this would take few seconds).

2. Right-click the Oled_test folder and select Run as->run configurations, as shown in the configuration (note stidio connection configuration when the port number is configured according to your computer). Click Apply, and then click Run. That is, run oled_test application on the ARM processor.

Run the results and see the following message on the OLED screen:

At this point, the experiment is complete.

Try different typography to write the document.

If a classmate wants the OLED IP core, comment on me.

Xilinx Vivado Usage Details (5): Call the user-defined IP core of the encapsulated