(10) Use of FSMC in Stm32 (for LCD)

FSMC full Name "Static memory controller".

With the FSMC controller, the fsmc_a[25:0 provided by FSMC can be used as the address line, and the fsmc_d[15:0 provided by FSMC] as the data bus.

(1) When the storage data is set to 8 bits (fsmc_nandinitstructure.fsmc_memorydatawidth = fsmc_memorydatawidth_8b)

Address fsmc_a[25:0], data bit corresponding to fsmc_d[7:0]

(2) When the storage data is set to 16 bits (Fsmc_nandinitstructure.fsmc_memorydatawidth = fsmc_memorydatawidth_16b)

Address fsmc_a[24:0], data bit corresponding to fsmc_d[15:0]

The FSMC consists of 4 modules:

(1) AHB interface (including FSMC configuration register)

(2) Nor Flash and Psram controllers (when the LCD is driving the LCD is like a psram with only 2 16-bit storage space, one is the data RAM and one is the cmd RAM)

(3) NAND Flash and PC Card controllers

(4) External device interface

Note : FSMC can request AHB for data width operation. If the data width of the AHB operation is greater than the width of the external device (nor or NAND or LCD), the FSMC splits the AHB operation into several contiguous, smaller data widths to accommodate the data width of the external device.

FSMC the address image of the external device starts at 0x6000 0000 and ends at 0x9fff FFFF, with a total of 4 address blocks and 256M bytes per address block. As can be seen, each address block is divided into 4 sub-address block, size 64M. For nor's address image, we can select haddr[27:26] to determine which 64M sub-address block is currently in use, such as the next page table. And these four pieces of storage block of the chip selection, then use Ne[4:1] to select. The data Line/Address line/control line is shared.

NE1->bank1 ne2->bank2 Ne3->bank3 ne4->bank4

If the NE1 is connected,

Nor/psram 64M per small block

First BLOCK: 6000 0000h--63ff ffffh (data length is 8-bit case, determined by address line fsmc_a[25:0], data length is 16-bit case, is determined by address line fsmc_a[24:0]

Second block: 6400 0000h--67ff FFFFH

Second block: 6800 0000H--6BFF FFFFH

Third block: 6c00 0000h--6fff FFFFH

Note: The haddr here is an internal AHB address line that needs to be converted to an external device, and each address corresponds to a byte cell. Therefore, if the address width of the external device is 8 bits, then haddr[25:0] corresponds to STM32 's CPU pin fsmc_a[25:0] One by one, which can access up to 64M bytes of space. If the address width of the external device is 16 bits, then haddr[25:1] corresponds to STM32 's CPU pin fsmc_a[24:0] one by one. When applied, the FSMC_A bus can be connected to the address bus pins of the memory or other peripherals.

Example: stm32f10xx fcms control LCD Driver

The FSMC provides all the LCD controller signals:
Fsmc_d[16:0]?? 16bit Data Bus
Fsmcnex: Assigned to nor 256M, divided into 4 zones, each area is used to allocate a peripheral, the four peripheral chips are divided into ne1-ne4, the corresponding pin is: pd7-ne1,pg9-ne2,pg10-ne3,pg12-ne4
FSMC NOE: Output Enable, connect the RD PIN to the LCD.
FSMC nwe: Write enable, connect the LCD's rw foot.
FSMCAX: Use the Address line selected between the LCD display RAM and the register, that is, the line used to select the RS pin of the LCD, the line can be any line of the address line, Range: fsmc_a[25:0].
Note: rs = 0 o'clock means read/write registers; rs = 1 indicates read and write data ram.
Example 1: Select nor the first storage area, and use FSMC_A16 to control the LCD's RS pin, then we access the LCD display RAM base is 0x60020000, access to the LCD register address is: 0x6000 0000. Because the data length is 16bit, so fsmc_a[24:0] corresponds to haddr[25:1] so display the base address of RAM =0x60000000+2^16*2=0x60000000+0x2 0000=0x60020000
Example 2: Select nor of the fourth storage area, using the Fsmc_a0 control LCD's RS foot, the access LCD display RAM base address is 0x6c000002, access to the LCD register is: 0x6c00 0000.

Cases:

Fsmc_d[15:0], even 16bit data cable; FSMC_NE1: only BANK1 available
FSMC NOE: Output Enable
FSMC NEW:FSMC Write enable
FSMC Ax: Connecting RS, usable range fsmc_a[24:0]

Generally use the mode B to do the LCD interface control, does not apply the external expansion mode. and read and write operations in the same sequence. In this case, we need to use three parameters: Addset,datast,addhold. These three parameters are set in the in-place domain FSMC_TCRX.
When the frequency of the HCLK is 72MHZ and mode B is used, the following timing is available:
Address Settling time: 0x1
Address hold Time: 0x0
Data Settling Time: 0x2
Note: Here address to establish the address to keep the data established three times do not know how to set out ..... I set it according to the experience of others. Master know this setting different what difference, please advise, thank you:)

* ******************************************************************************
* Function Name: lcd_ctrllinesconfig
* Parameters: None
* Return: None
* Function: Configure LCD control port line, FSMC pin is set to multiplexing function
*/
Voidlcd_ctrllinesconfig (void)
{
Gpio_inittypedef gpio_initstructure;


* RCC enable FSMC clock directly from the AHB clock, that is, HCLK, there is no crossover. The control bit is the Fsmcen bit in Rcc_ahbenr
Rcc_ahbperiphclockcmd (RCC_AHBPERIPH_FSMC, ENABLE);

Gpio Port and Afio port clock from APB2, i.e. PCLK2, control bit is iopxen and Afioen bit in Rcc_apb2ern
Rcc_apb2periphclockcmd (Rcc_apb2periph_gpiod | rcc_apb2periph_gpioe| Rcc_apb2periph_afio, ENABLE);


Gpio_initstructure.gpio_pin = Gpio_pin_0 | gpio_pin_1 | gpio_pin_4| Gpio_pin_5 | gpio_pin_7 | Gpio_pin_8 | Gpio_pin_9 | gpio_pin_10 | Gpio_pin_11 | gpio_pin_14 | Gpio_pin_15;
Gpio_initstructure.gpio_speed = Gpio_speed_50mhz;
Gpio_initstructure.gpio_mode = gpio_mode_af_pp;
Gpio_init (Gpiod, &gpio_initstructure);


Gpio_initstructure.gpio_pin = gpio_pin_7 | Gpio_pin_8 | gpio_pin_9| gpio_pin_10 | Gpio_pin_11 | Gpio_pin_12 | gpio_pin_13 | gpio_pin_14 | Gpio_pin_15;
Gpio_initstructure.gpio_speed = Gpio_speed_50mhz;
Gpio_initstructure.gpio_mode = gpio_mode_af_pp;
Gpio_init (Gpioe, &gpio_initstructure);


Gpio_initstructure.gpio_pin = gpio_pin_0;
Gpio_init (Gpiof, &gpio_initstructure);


Gpio_initstructure.gpio_pin = Gpio_pin_12;
Gpio_init (Gpiog, &gpio_initstructure);
}

The signal line for the FSMC output is set to multiplexed push-pull output mode (Alternate function Push-pull).
How to set the signal line for FSMC input is not clear,??????
*FSMC Self-setting
The FSMC itself is set to two pieces, one is the control mode setting, is for the FSMC_DCR setting, the other one is the reading and writing timing setting, is for the FSMC_DTR setting.

The Norflash and Psram operation Timing Settings-----The settings of the FSMC_DTR.


void Lcd_fsmcconfig (void)
{
Fsmc_norsramtiminginittypedef p;
P.fsmc_addresssetuptime = 1;
P.fsmc_addressholdtime = 1;
P.fsmc_datasetuptime = 20;
p.fsmc_busturnaroundduration = 0;
p.fsmc_clkdivision = 0;
P.fsmc_datalatency = 1;
P.fsmc_accessmode = fsmc_accessmode_a;

The following paragraph is the setting of the control mode----FSMC_DCR

Fsmc_norsraminittypedef fsmc_norsraminitstructure;

Fsmc_norsraminitstructure.fsmc_bank = fsmc_bank1_norsram1;


Fsmc_norsraminitstructure.fsmc_dataaddressmux =fsmc_dataaddressmux_disable;

Fsmc_norsraminitstructure.fsmc_memorytype =fsmc_memorytype_sram;

Fsmc_norsraminitstructure.fsmc_memorydatawidth =fsmc_memorydatawidth_16b;

Fsmc_norsraminitstructure.fsmc_burstaccessmode =fsmc_burstaccessmode_disable;

Fsmc_norsraminitstructure.fsmc_waitsignalpolarity =fsmc_waitsignalpolarity_low;

Fsmc_norsraminitstructure.fsmc_wrapmode =fsmc_wrapmode_disable;

Fsmc_norsraminitstructure.fsmc_waitsignalactive =fsmc_waitsignalactive_beforewaitstate;

Fsmc_norsraminitstructure.fsmc_writeoperation =fsmc_writeoperation_enable;

Fsmc_norsraminitstructure.fsmc_waitsignal =fsmc_waitsignal_disable;

Fsmc_norsraminitstructure.fsmc_extendedmode =fsmc_extendedmode_disable;

Fsmc_norsraminitstructure.fsmc_asyncwait =fsmc_asyncwait_disable;

Fsmc_norsraminitstructure.fsmc_writeburst =fsmc_writeburst_disable;

Fsmc_norsraminitstructure.fsmc_readwritetimingstruct =&p;
Fsmc_norsraminitstructure.fsmc_writetimingstruct = &p;

Fsmc_norsraminit (&fsmc_norsraminitstructure);

Fsmc_norsramcmd (fsmc_bank1_norsram1, ENABLE);
}

Summary: the address map used here belongs to BANK1 nor/psram1 so the data base is 0x6c000000 and the cmd address is 0x6c000002 because the LCD's RS is connected to fsmc_a0. When the FSMC is configured, it is OK to write data or cmd as long as the two addresses are manipulated.

(10) Use of FSMC in Stm32 (for LCD)