20145239 "Information Security system Design Fundamentals" 6th Week Study Summary

20145239 "Information Security system Design Fundamentals" The 6th Week study summary textbook Learning content Summary

Y86 Instruction Set architecture

• Y86: Includes defining various state elements, instruction sets and their encodings, a set of programming specifications, and exception event handling.

• Programmer Visible State

  1. Each instruction in the Y86 program reads or modifies portions of the processor state.

  2, can access and modify program register, condition code, program counter and memory, status code indicates whether the program is working properly.

  • 8 Program Registers:%eax,%ECX,%edx,%EBX,%esi,%edi,%esp,%EBP. Each program register stores one word. %ESP is used as a stack pointer by the stack, stack, call, and return instructions.
  • There are 3 one-bit conditional codes: ZF, SF, of, and they keep information about the effects of recent arithmetic or logic directives.
  • The program counter (PC) holds the address currently being executed.
  • Memory: A large byte array that holds programs and data.

• Y86 directive

  1. Only four-byte integer operations are included.

  2, instruction encoding length from 1 bytes to 6 bytes, an instruction contains a single-byte instruction indicator, may contain a single-byte register indicator, may also contain a four-byte constant number.

  The field FN indicates an integer operation (OPL), Data movement condition (CMOVXX), or branch condition (JXX).

  All values are in hexadecimal notation:
  

  3. IA32 's MOVL instruction is divided into 4 different directives: IRMOVL, RRMOVL, MRMOVL and RMMOVL. Indicate the source and destination formats, respectively:

  源操作数：立即数i、寄存器r、存储器m目的操作数：寄存器r、存储器m

  Attention:

  （1）两个存储器传送指令中的存储器引用方式是简单的基址和偏移量形式。（2）在地址计算中，不支持第二变址寄存器和任何寄存器值的伸缩。（3）不允许从一个存储器地址直接传送到另一个存储器地址。也不允许将立即数传送到存储器。

  4, 4 integer operation instruction: Addl, Subl, Andl, Xorl

  5, 7 jump Commands (JXX): jmp, Jle, JL, je, jne, Jge, JG

  6.6 Conditional Delivery Instructions (CMOVXX): Cmovle, CMOVL, Cmove, Cmovne, Cmovge, CMOVG

  Note: The value of the destination register is updated only if the condition code satisfies the required constraint.

  7, the call command will return the address into the stack, and then skip to the destination address. The RET instruction is returned from such a procedure call.

  8, PUSHL and POPL instructions are implemented into the stack and out of the stack. The behavior of the processor is not deterministic when executing the PUSHL and POPL directives because the registers to be placed on the stack are modified by the same instruction. There are usually two kinds of conventions:

  （1）压入/弹出%esp的原始值（2）压入/弹出%esp-/+4后的值

  9, halt instruction to stop the execution of instructions. For Y86, executing the halt instruction will cause the processor to stop and set the status code to HLT.

• Instruction encoding

  1. The first byte of each instruction indicates the type of instruction. This byte is divided into two parts, each part 4 bits: the height 4 bits is the code part, the low 4 bit is the function part. function values are only useful if a single set of related directives is shared with one code.

  （1）整数操作里代码部分均为6，功能部分区分addl，subl，andl，xorl（2）分支指令里代码部分均为7（3）传送指令里代码部分均为2

  Each of the 2, 8 program registers has a corresponding register identifier for the 0~7:
  

  The program register exists in a register file, which is a small, random-access memory with the Register ID as the address. The ID value 0xF is used when it is necessary to indicate that no registers should be accessed.

  3, branch instruction and call instruction do not have register operand, there is no register indicator byte.

  The IRMOVL, PUSHL, POPL directives require only one register operand and the other register to indicate subscript character to 0xF.

  4. An important property of the instruction set is that the byte encoding must have a unique interpretation.

  All integers are encoded using a small-end method. These bytes appear in reverse order when the instruction is written in disassembly format.

• Y86 exception

  When an exception occurs, the Y86 processor stops running instructions, and you can call an exception handler to make it more complete.

  Y86 Status Code:
  

• Y86 Program

  1. The main difference between Y86 code and IA32 code:

   （1）Y86可能需要多条指令来执行一条IA32指令所完成的功能。

       （2）Y86没有伸缩寻址模式。

2. To "." The opening words are assembly commands, which they tell the assembler to adjust the address. The only tool for creating Y86 code is the assembler.

• Instruction Set Simulator Yis

Simulates the execution of a Y86 machine code program without attempting to emulate the behavior of any specific processor implementation.

Logic design and hardware control Language HCL

• Three main components are required to achieve a digital system:

  （1）计算对位进行操作的函数的组合逻辑（2）存储位的存储器元素（3）控制存储器元素更新的时钟信号

• Logic gates

  AND     &&OR      ||NOT     !

  The logic gate operates only on the number of individual bits, not the entire word. Once the input of a door changes, in a short time, the output will follow the change.

• Combinational Circuits and HCl Boolean expressions

  1, the logic gate is combined into a network to build the limit of the computational block (Combinational Circuit).

  Attention:

  • The output of more than two logic gates cannot be connected together, otherwise the line signal may be contradictory, resulting in an illegal voltage or circuit failure.
  • This network must be non-ring, otherwise it will cause ambiguity in network computing.

  2. The difference between logical expressions in combinational logic circuits and C language:

  • The output of the combined circuit continuously responds to input changes, and the C language expression is evaluated only when it is encountered during execution.
  • The logical expression of C allows the argument to be any integer, 0 is false, and any other value 0 is true, and the logic gate operates only on the bit values 0 and 1.
  • The logical expression of C may be partially evaluated (the first parameter can determine the result without evaluating the second one).

• Combination of Word-level circuits and HCl integer expressions

  1. All word-level signals are declared as int and do not specify the size of the word.

  2, stooped class circuit, the medium thickness of the line to represent each bit of the line of carrying words, with dashed lines to indicate the result of a Boolean signal.

  3. Multiplexing functions

  通用格式：[   select_1(布尔表达式):expr_1(整数表达式)   select_2：expr_2    ......   select_k：expr_k]

  The selection expression is evaluated sequentially, the first case with a value of 1 is selected, and the selection expression allows for non-mutex.

• Collection relationships

  in {iexpr1,iexpr2,...,iexprk}

  The values tested iexpr and matched values IEXPR1~IEXPRK are integer expressions.

• Memory and Clock

1, sequential Circuit: a state, and in this state to calculate the system.

Two types of memory devices:

• Clock Register (register): a single bit or word is stored, and the input value is loaded with the clock signal control register. (Save program counter PC, Condition code CC and program status stat)
• Random access Storage (storage): Save multiple words, use the address to choose which word to read/write. (Store program Data)

2, the processor also includes another read-only memory, used to read instructions. In most real systems, however, the two memories are combined into a two-port memory: one for reading instructions and one for reading or writing data.

Sequential implementation of Y86

• SEQ Sequential processor

  On each clock cycle, SEQ executes all the steps required for a complete instruction.

• Organize the processing into stages

  Six basic stages:

  • Read the instruction byte from memory, address the value of the program counter PC
  • Decoding reads a maximum of two operands from the register, resulting in Vala or valb
  • Executing an arithmetic/logical unit either executes the operation specified by the instruction, computes the valid address of the memory reference, or increases or decreases the stack pointer. The resulting value is Vale.
  • The data is written to memory or read from memory, and the value read is Valm.
  • Write-back can write up to two results to a register file
  • Update PC to set the PC as the address of the next instruction

• SEQ Hardware structure

  SEQ Abstract View Drawing conventions:

  浅灰色方块表示硬件单元控制逻辑块是用灰色圆角矩形表示的线路的名字在白色椭圆中说明宽度为字长的数据连接用中等粗度的线表示宽度为字节或更窄的数据连接用细线表示单个位的连接用虚线

• The implementation of the

• Seq timing

  Seq includes the combined logic (no timing or control required) and two memory devices:

  • Clock Register program counter and Condition code register

  • Random access memory register file, instruction memory and data memory

      instruction memory is used only to read instructions (which can be considered as combinatorial logic) the condition code register only loads the data memory when executing the integer operation instruction only in the execution RMMOVL, PUSHL or call when writing to a register file two write ports allow two program registers to be updated per clock cycle. (Special register id 0xf indicates that this port should not perform a write operation)     

• Implementation of the SEQ phase

  1, take the finger stage: The address of the first byte of the PC, read 6 bytes at a time

  icode   控制逻辑块计算指令ifun    功能码

  Three-bit signals (based on icode values)

  instr_valid     发现不合法的指令need_regids     包含寄存器指示符字节码need_valC       包括常数字码

  The latter five bytes are the combined encoding of the Register designator byte and the constant number.

  2. Decoding and writing back phase

  All need to access the register file, according to the case of four ports, determine which register should be read to generate the signal Vala, Valb.

  Register file, supports simultaneous two reads and two writes, each port has an address connection (register ID) and a data connection (32 lines), can be used as the output word of the register file, but also as his input word.

  3, the implementation phase:

  • Includes arithmetic/logic unit (ALU), output is Vale signal: ALU is usually used as adder
  • Includes the condition code register: 0 per run, sign, overflow, generate signal set_cc

  4, the visit stage: Read or write program data

  Two data blocks generate the memory address and the value of the memory input evidence, and two generate control signals indicating whether to read or write.

  When the read operation is performed, the data memory generates VALM.

  Based on Icode,imem_error,instr_valid,dmem_error, the status code stat is calculated from the result of the instruction execution.

  5. Update PC Stage

  Generates a new value for the program counter, depending on the type of instruction and whether to select the branch, the new PC may be valc, Valm, or Valp.

Y86 Simulator Installation

The installation steps refer to the 20145218 blog: http://www.cnblogs.com/senlinmilelu/p/5985966.html#3538763

• Install the Bison and flex lexical analysis tools and enter them in the terminalsudo apt-get install bison flex

• Download Sim Decompression: wget Http://labfile.oss.aliyuncs.com/courses/413/sim.tar

• The graphical interface requires the installation of TCL/TK, which is entered in the terminalsudo apt-get install tcl8.5-dev tk8.5-dev tcl8.5 tk8.5

• Locate the makefile file in the extracted Sim folder, make the following changes and save

Guimode=-dhas_gui//Will # Remove

tklibs=-l/usr/lib/-ltk8.5-ltcl8.5//Plus 8.5

tkinc=-i/usr/include/tcl8.5//change Isystem to uppercase I, plus tcl8.5 at the end

• Compile in the Sim folder right-click to open in Terminal, entermake clean;make

(The main function of make clean is to remove the suffix. yo files)

• Use Cat to view the compiled Asuml.yo file after make all.

This week's code hosting

Links: Https://git.oschina.net/929210354/Linux

Learning progress Bar /Cumulative) new/cumulative)

	lines of code (new	Blog volume (	Learning time (new/cumulative)	Important growth
Goal	3500 rows	30 Articles	400 hours
First week	100/100	1/1	20/20
Second week	200/300	1/2	30/50
Third week	100/400	1/3	28/78
Week Five	60/460	1/4	20/98
Week Six	200/660	1/5	21/119

Resources

• Getting Started with Linux basics
• Fundamentals of C language development under Linux

20145239 "Information Security system Design Fundamentals" 6th Week Study Summary