(5.2) Uboot detailed--Power saving mode (pan-out)

(5.2) Uboot detailed--Power saving mode (pan-out)

This article will uboot the power-saving mode analysis, the content described here and uboot start in fact, if you care about Uboot startup process, you can skip this section and the following subsections, directly to the 6th chapter.

Power-saving mode and CPU operating mode (abnormal) In fact, the relationship is not small, the power-saving mode is mainly based on the clock to classify, because the peripheral work must be clock, when the peripheral clock is stopped, the corresponding peripherals will also stop working, So the power-saving management is based on the control whether to provide the corresponding equipment clock or power to achieve the purpose of energy saving.

ARM has four power-saving modes:

Normal mode: in this mode, all peripherals and CPUs will be provided with a clock, when all the peripherals are turned on, the power consumption will be maximized, we can also be programmed to control which peripherals are provided, such as a timer does not need to use, The user can stop providing the clock to this device by setting the corresponding bit of the Clkcon register to achieve the purpose of saving energy.

Slow mode: that is, turn off the PLL mode, in this mode is not a multiplier operation, unlike normal mode, the slow mode is by using an external clock (XTIPLL or EXTCLK) as the input clock, the clock is not locked loop, The frequency will be less than (if there is a setting of CLKSOLW) or equal to the external clock size.

Idle mode: This mode provides clocks to all peripherals, but does not provide CPU cores, which can reduce the power consumption of the CPU cores, but when an interrupt request arrives, the CPU wakes up from idle mode.

sleep mode: This mode not only shuts down the CPU core clock, but also shuts down and CPU cores integrated in other logic units inside the CPU, such as the internal watchdog and on-chip memory, but provides the clock to the on-chip wake-up unit. Wake-up sleep mode requires two conditions, one is to provide current to the on-chip wake-up unit, and the other is to provide current to other units on the chip, and this second power supply can control the other units on the chip power supply and closing. In sleep mode, you can wake up with eint[15:0] or RTC alarm interrupt.

The Power management module can be controlled by software to achieve the purpose of reducing system power consumption. Modules related to power management include phase-locked loop (PLL), clock control, and wake-up units. S3C2440A has 4 power-saving modes, followed by descriptions of these 4 modes. The 4 mode is not free to switch, please see the switch to 4 modes.

In general mode, all basic peripherals are likely to be fully functional, including power management module, CPU core, bus controller, memory manager, interrupt Controller, DMA and external controller, etc., but to each peripheral clock, processing basic peripherals can be controlled by the software to stop the supply of clocks.

In idle mode, the clock that is delivered to the CPU core is stopped, in addition to the bus controller, memory controller, interrupt controller and power management module, if you want to exit this idle mode, you can set the EINT[23:0],RTC clock interrupt or other interrupt (note that if the Gpio module is not turned on, Eint will not be in effect)

In slow mode, energy saving is achieved by using a lower clock and eliminating the consumption of the phase-locked loop module. The phase-locked loop is not working, and if you need to set the size of the FCLK, you need to set the Clkslow register, but HCLK and PCLK still use the CLKDIVN register to set the crossover.

When switching from slow mode to normal mode, the PLL is turned on, and the externally supplied clock still passes a lock time to stabilize the output, so it takes at least 300us of time to output a stable clock when the PLL is started, and in this 300us, The size of the FCLK clock is still the size of the slow clock, note that it is not necessarily equal to the size of the external clock, since it is possible to set the Clkslow register in slow mode.

We can turn slow mode on or off by setting the Enable SLOW mode bit of the Clkslow register.

In sleep mode, the CPU and all internal logic units (processing wake-up units) will not consume power, wake-up sleep mode requires two separate power supplies, a power supply that provides current to the wake-up unit, and a power supply that provides current to all internal logic units (excluding wake-up units) and CPUs. In sleep mode, the second power supply will be cut off. If you are waking from sleep mode, you can interrupt by triggering eint[15:0] or RTC clock. Here's what you need to do to get into sleep mode:

1. Set the Gpio for sleep mode

2. Set the INTMSK register to block all interrupts

3. Set the appropriate wake-up source, including the RTC clock. (set Intmsk to not block wake-up feeds)

4. Set the USB pads to suspend mode (MISCCR[13:12]=11B)

5. Save some important values in the Gstatus[4:3] register, and the values in these registers will be saved in sleep mode.

6. Set the pull-up bus on the data bus misccr[1:0]

7. Stop the LCD by clearing the Envid bit of the LCDCON1

8. Read the Rrefresh and Rclkcon registers to populate the TLB

9. Let SDRAM enter Self-refresh mode by setting refresh[22]=1b

10. Wait until the Self-refresh of SDRAM works

11. Set MISCCR[19:17]=111B, which is the SDRAM signal (SCLK0,SCLK1 and SCKE) protected in sleep mode

12. Place the Clkcon's sleep mode position 1

Tip: If the system is from NAND boot mode, the hardware pin (eint[23:21]) must be set to input so that the system can be started when waking from sleep mode.

The above describes how to enter sleep mode, below will explain how to wake up from sleep mode.

1. If any of the wake-up sources are triggered, the internal reset signal will be declared, similar to the external nreset pin, the reset interval is determined by the internal 16-bit counting logic unit, and the Reset declaration time is calculated as: TRST = (65535/xtal_ Frequency).

2. Check gstatus2[2] To determine whether the power increase caused by the wake-up source occurs in sleep mode

3. Release the signal protection to SDRAM by setting the MISCCR[19:17]=000B

4. Configuring the SDRAM Memory Manager

5. Wait for SDRAM Self-refresh to be released

6. Content saved in Gstatus[3:4] can be used

7. Check the SRCPND register and the Eintpend register

Above this graph is the power management diagram in sleep mode, when in sleep mode, only the peripheral and internal power control unit is working, and the CPU and other internal logic units are not power, The power supply to the internal power control unit is vddalive. As you can see, there are two ways to send a signal to an internal power management unit, one is the RTC alarm, the other is Eint, and when the signal is received, the internal power control unit sends a signal to the Pwren calibrator, Then decide what kind of power to supply the internal unit.

is the datasheet of the Clkcon register, which can specify battery saver mode and set trigger interrupt

is the datasheet of the Clkslow register, which can be set according to FCLK,HCLK and PCLK clock

About the CLKDIVN register before, it's not listed here.

Summary: Here is a simple analysis of some of the power-saving mode of the content, will continue to write a bit outside, to understand the RTC and PWM Things

(5.2) Uboot detailed--Power saving mode (pan-out)