6. in-depth understanding of computer system notes: storage hierarchy and storage technology (1)

1. If yourProgramThe required data is stored in the CPU register, so they can be accessed within zero period of execution. If it is stored in High-Speed buffering, 1 ~ 10 cycles. If it is stored in the primary storage, 50 ~ 100 cycles. If it is stored on a disk, it takes about 20000000 cycles.

2. random access memory (RAM, random-access memory) is divided into two types: static and dynamic. Static RAM (SRAM) is faster but more expensive than dynamic RAM (Dram. SRAM is used as high-speed cache memory, that is, it can be on the CPU chip or not on the CPU chip. DRAM is used as the frame buffer of the primary storage and graphics system.

3. Static RAM

SRAM stores each bit in a bistable memory unit (cell. Each unit is implemented using a six transistor circuit. One Property of this circuit is that it can be kept unrestricted in one of two different voltage configurations or states. Any other status is unstable.

Due to the bistability of SRAM, as long as there is electricity, it will always maintain its value, even if there is interference, such as electronic noise, when the interference is eliminated, the circuit can also be restored to a stable value.

4. Dynamic RAM

DRAM stores each bit to charge the capacitor. The capacitance is about 30 × 10.-15F.

Various factors that leak current may cause DRAM units to be in the range of 10 ~ The charge is lost within 100 milliseconds. The clock cycle of computer operation is measured in nanoseconds.

In the computer field, DRAM array units are often called cells, and circuit designers tend to call them words ). This is called supercell.

We can see that the disadvantage of two-dimensional array organization is that the address must be sent in two steps, which increases the access time.

5. Dual Inline Memory Module (dimm) with 168 pins, which transmits data to the storage controller and transmits data from the storage controller in 64 bits; single Inline Memory Module (SIMM) with 72 pins, which transmits data in 32-bit segments.

6. SDRAM (synchronous DARM, synchronous DRAM) uses the rising edge of the same external clock signal as the drive memory to replace many of these control signals.

Ddr sdram (double data-rate synchronous DRAM, double data count rate synchronous DRAM ). DDR sdarm is an increase in SDRAM. It uses the two edges of the clock as the control signal to double the dram speed.

7. EEPROM (Electronic erasable prom), similar to DPROM, but it does not need a physically independent programming device, so it can be programmed directly on the printed circuit card. The number of times that the EEPROM can program can be up to 10 E5 times. Flash memory is a small non-volatile memory. It is based on EEPROM and supports plug-in.

8. programs stored in ROM devices are usually called firmware ).

9. Access the primary storage

Read transaction transfers data from the primary memory to the CPU; write transcation transfers data from the CPU to the primary memory.

A bus is a set of parallel wires that can carry address, data, and control signals.

1) read transaction statement

Movl A, % eax;

The CPU places address a on the memory bus-> the main memory reads a from the bus, receives the word X, and then places X on the bus-> the CPU reads the word X from the bus, and copy it to the Register eax.

2) Write transaction statements

Movl % eax,

The CPU places address a on the memory bus, and the master memory reads the address, waiting for receiving the data word-> the CPU places the data word y on the master road-> the master memory reads the data word y from the bus, and store it in address.

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