80x86 protection mode and its programming (I.)

80x86 system registers and system directives

1. Flag Register (EFLAGS)

Flag Register EFlags The meaning of the flag bit is as follows:

The TF bit 8 is a trace flag, which can be used to initiate a single step execution for a debug operation when the bit is set. Single step is forbidden when resetting. In single-step execution, the processor generates a debug exception after each instruction execution, so that we can observe the state of the executing program after each instruction executes.

IOPL bit 13-12 at the I/O privilege level (I/O Privilege levels) field. This field indicates the I/O privilege level IOPL of the currently running program or task. The CPL for the current task or program must be less than this IOPL to access the I/O address space. Only if the CPL bit privilege Level 0 o'clock, the program can use Popf or iret instructions to modify this field, IOPL is also the control of the IF flag modification of one of the mechanisms

NT bit 14 is a nested task flag (Nested Task). It controls the link relationship between the interrupted task and the calling task. When a call instruction, interrupt, or exception is used to perform a task invocation, the processor sets the flag and the processor checks for and modifies the NT flag when it is returned from a task through the iret instruction. This flag can also be modified using the POPF/POPFD directive, but changing the state of the flag in the application produces unexpected exceptions

The RF bit 16 o'clock recovery flag (resume flag). This flag is used to control the processor's response to a breakpoint directive. When set, this flag temporarily disables the breakpoint instruction from generating debug exceptions, and when the flag is reset, the breakpoint instruction will produce an exception. The primary function of RF is to allow the debug exception to be re-executed after an instruction. When the Debug software uses the IRETD directive to return the interrupted program, the RF flag in the EFlags content on the stack needs to be set to prevent the instruction breakpoint from causing another exception, and the processor automatically clears the flag after the instruction returns, allowing the instruction breakpoint exception again.

VM bit 17 is a virtual-8086-way flag, when the flag is set, a new virtual-8086 mode is turned on, and when the flag is reset, it returns to protected mode

Memory Management Registers

The processor provides 4 memory management registers (GDTR, LDTR, IDTR, and TR) to specify the base address of the system tables used by the segmented memory manager, which contains important information about the fragmentation mechanism. The GDTR, IDTR, and LDTR are used to address segments that hold descriptor data, and TR is used to address a particular task state segment of TSS, the TSS segment, which contains important information about the current execution of the task. See, the processor provides specific instructions for loading and saving these registers.

1. Global Descriptor Descriptor Register (GDTR)

The GDTR register is used to hold the linear base address (32-bit) and table-length values (16-bit) of the Global Symbol Description table (GDT). Base site Specifies the address in the linear address space of byte 0 in the GDT table, the length of the table indicates the byte length value of the GDT table, instruction Lgdt and SGDT respectively facilitates and the contents of the GDTR register are saved. After the machine has just been power-up or the processor is reset, the base address is set to 0 by default, and the table length is set to 0xFFFF. In the protection mode initialization process China must load a new value for GDTR.

2. Interrupt Descriptor Descriptor Register IDTR

Similar to GDTR, the IDTR register is used to hold the 32-bit linear base address and 16-bit table length values of the interrupt descriptor. The instruction Lidt and Sidt respectively use facilitates and save the contents of the interrupt Descriptor descriptor. After the machine has just been power-on or the processor is reset, the base address is set to 0 by default and the length value is set to 0xFFFF

3. Local Descriptor Descriptor Register LDTR

The LDTR is used to store a 32-bit linear base address, 16-bit segment length limit, and descriptor attribute values for the local descriptor descriptor LDT. Instructions Lldt and Sldt are used to load and save the segment descriptor portion of the LDTR register, and the segment containing the LDT table must have a segment description in the GDT table entry

4. TR Task Register

The TR register is used to hold the 16-bit segment selector, 32-bit base address, and 16-bit segment length and descriptor attribute values for the TSS segment of the current task. It refers to a TSS type in the GDT table into the descriptor, the instruction ltr and STR respectively with facilitates and the segment selector portion of the Save TR Register.

Control Register

The control registers (CR0, CR1, CR2, CR3) are used to control and determine the operating mode of the processor and the characteristics of the current execution of the task, as shown in the CR0 contains system control flags that control the operating mode and state of the processor; CR1 reserved, CR2 contains linear addresses that cause errors The CR3 contains the physical memory base address of the page catalog table, so this register is also referred to as the page directory base register (PDBR).

1, CR0 in the coprocessor control bit

The 4 bit bits in the CR0: the extension type bit ET, the task switch bit TS, the simulation bit EM and the mathematical presence bit MP are used to control the operation of the 80x86 floating point (math) coprocessor.

The ET is the CR0 bit 4 is the extension type flag, when the flag is 1 o'clock, indicates that the system has 80387 coprocessor present and uses the 32-bit coprocessor protocol. When et=0 indicates that the 80287 coprocessor is used. If the emulation bit is em=1, the bit is ignored. During a processor reset operation, ET is initialized to indicate the type of coprocessor used in the system. If there is 80387 in the system, it is set to 1, otherwise if there is a 80287 or no coprocessor, et is set to 0

TS is the 3rd bit of CR0, the task-switched (task switched) flag, which is used to postpone the coprocessor content when the task switch is saved until the new task actually executes the coprocessor directive. The processor sets the flag on each task switch and tests the flag when it executes the coprocessor instruction.

If the TS flag is set and the EM flag of CR0 is 0, a device does not exist (a DNA) exception before any coprocessor instructions are executed. If the TS flag is set but the MP and EM flags for CR0 are not set, the device does not have an exception before executing the coprocessor directive wait/fwait. If the task has never used a coprocessor, then the corresponding coprocessor context is not saved.

EM is the CR0 2nd bit, the simulation flag, when the location is set, indicating that the processor does not have an internal or external coprocessor, the execution of the coprocessor instruction will cause the device no exception, when cleared, the collaboration has a coprocessor, set this flag can force all the floating point instruction using software to simulate.

The MP is the bit 1 of the CR0 is the monitor coprocessor flag (monitor coprocessor or math present) flag, which controls the interaction of the wait/fwait instruction with TS. If Mp=1, Ts=1, then the wait instruction will produce a device without an exception. If mp=0, the TS flag does not affect the execution of wait

2. Protection control bit in CR0

The bit 0 of the PE CR0 is the Enable protection flag, when the bit is set, the protection mode is turned on, and the real address mode is entered when reset. This flag only turns on segment-level protection and does not have a paging mechanism enabled. To enable the paging mechanism, both the PE and PG flags are placed

The bit 31 o'clock paging flag bit of PG CR0, which opens the paging mechanism when the bit is set, and disables the paging mechanism when reset, where all linear addresses are equal to the physical address. The PE flag must be turned on or at the same time before this flag is turned on, that is, for the paging mechanism, the PE and PG flags are set

WP for Intel 80486 or more of the CPU,CR0 16-bit is a write protection flag, when the flag is set, the processor will prohibit the super-user program (such as the privilege Level 0 program) to the user-level read-only page write operation, when the bit is reset, the reverse. This identity facilitates the UNIX class operating system to implement write-time replication technology when the process is created.

NE for Intel 80486 or above, bit 5 of CPU,CR0 is the coprocessor fault (numberic error) flag. When this flag is set, an internal reporting mechanism for X87 coprocessor errors is enabled, and if the bit is reset, the X87 coprocessor Error Reporting mechanism is used in the form of a PC. The math co-processor X87 error is ignored when NE is reset and the Ignne input pin of the CPU is signaled

Enable protected mode PE bit and turn on paging PG bit for control of segmentation and paging mechanism respectively

CR2 and CR3

CR2 and CR3 for paging mechanism, CR3 contains physical address for Page Catalog table page

80x86 protection mode and its programming (I.)