A more interesting piece of code--Introduction to the new Increment statement in System Verilog

Many new amplitude statements are added to system Verilog, although they are only applicable to blocking amplitude, but are useful in some situations.

Here's an interesting piece of code that covers a few uses.

1 Package definitions;2typedef enum LOGIC [2:0] {ADD,SUB,MULT,DIV,SL,SR} opcode_t;3 typedef enum LOGIC {UNSIGNED, signed} operand_type_t;4 typedef union PACKED {5Logic [ at:0] U_data;6Logicsigned[ at:0] S_data;7 } data_t;8 typedef struct PACKED {9 opcode_t OPC;Ten operand_type_t Op_type; One data_t op_a; A data_t op_b; - } instruction_t; -Endpackage//Definitions the      -Import definitions::*;//Import package into $unit space -      - ModuleAlu (inputInstruction_t InStr,Outputdata_t alu_out); +Always_combbegin -         if(Instr.op_type = = signed)begin +Alu_out.s_data =Instr.op_a.s_data; AUnique Case(INSTR.OPC) atADD:alu_out.s_data + =Instr.op_b.s_data; -SUB:alu_out.s_data-=Instr.op_b.s_data; -MULT:alu_out.s_data *=Instr.op_b.s_data; -DIV:alu_out.s_data/=Instr.op_b.s_data; -SL:alu_out.s_data <<<=2; -SR:alu_out.s_data >>>=2; in             Endcase -             176SystemVerilog forDesign to               End +         Else begin -Alu_out.u_data =Instr.op_a.u_data; theUnique Case(INSTR.OPC) *ADD:alu_out.u_data + =Instr.op_b.u_data; $SUB:alu_out.u_data-=Instr.op_b.u_data;Panax NotoginsengMULT:alu_out.u_data *=Instr.op_b.u_data; -DIV:alu_out.u_data/=Instr.op_b.u_data; theSL:alu_out.u_data <<=2; +SR:alu_out.u_data >>=2; A             Endcase the         End +     End - Endmodule

Package,structure and some newly added assignment statements are used in the code.

Note that Always_comb is used here because these assignment statements are equivalent to blocking assignments.

A more interesting piece of code--Introduction to the new Increment statement in System Verilog