A simple RISC CPU design based on state machine

Directory one, what is the CPU? Second, RISC CPU structure

1. Clock Generator 2. Instruction register 3. Accumulator 4.RISC CPU arithmetic logic arithmetic Unit 5. Data Controller 6. State Controller 7. Program counter 8. Address multiplexer 9. Peripheral Module 10. Address Decoder

a.ram

b.rom

Third, RISC CPU components of the mutual connection relationship four, RISC CPU and its peripheral circuit five, RISC CPU addressing mode and instruction System VI, RISC CPU operation and timing body one, what is the CPU? The CPU is the abbreviation of the central processing Unit, which is the core part of the computer. Computer processing can be divided into two steps:

1. Data and programs (that is, sequence of instructions) are entered into the computer's memory.
2. Start the program from the address of the first instruction, get the desired result, and end the run. The role of the CPU is to coordinate and control the sequence of instructions of each part of the computer to execute the program, so that it is carried out methodically. Therefore, it must have the following basic functions:

• A) Take command: When the program is already in memory, first, according to the program entry address to remove a program, to issue a command address and control signal.
• b) Analysis instructions: that is, instruction decoding. is to analyze the currently obtained instruction, indicate what operation it requires, and produce the corresponding operation control command.
• c) Execution instruction: According to the "Operation command" generated by the analysis instruction, the corresponding operation control signal sequence is formed, and the function of each instruction is realized through the operation of the arithmetic, memory and input/output devices, including the processing of the result of the operation and the formation of the next instruction address.

Further refinement of its functionality can be summarized as follows:

1. Can decode the instruction and carry out the prescribed action;
2. Arithmetic and logic operations can be performed;
3. Can exchange data with memory, peripheral;
4. Provide the control required by the entire system;

Although the performance metrics and structural details of the various CPUs vary, the basic functionality they can accomplish is the same. By functional analysis, it is known that any one CPU internal structure should contain at least the following components:

1. Arithmetic Logic operation unit (ALU),
2. Accumulator
3. Program counters,
4. Instruction register, decoder,
5. Timing and control components.

RISC is the abbreviation for the thin instruction set computer (reduced instruction set computer). It is a kind of CPU that appeared in the 80 's, compared with the general CPU, it not only simplifies the instruction system, but also makes the structure of the computer simpler and more reasonable by simplifying the instruction system, thus improving the computing speed. From the way of implementation, the RISC_CPU differs from the general CPU in that its timing control signals form parts that are implemented using the hard wiring logic rather than the micro-programmed approach. The so-called hard wiring logic is the state machine and the combinational logic which is formed by the direct connection of the trigger and the logic gate, so the speed of the control sequence is much faster than that of the micro-program, because it eliminates the time to read the micro-instruction. RISC_CPU also includes these components, and the following is a detailed introduction to the design and simulation of a simplified RISC_CPU integrated VERILOGHDL model for instructional purposes. Second, RISC CPU structure RISC_CPU is a complex digital logic circuit, but the logic of its basic components is not complicated. It can be divided into eight basic components:

1. Clock generators
2. Instruction Register
3. Accumulator
4. RISC CPU arithmetic logic arithmetic unit
5. Data controller
6. State Controller
7. Program counter
8. Address multiplexer

The clock generator uses a foreign clock signal to divide the generation of a series of clock signals, sent to other parts as a clock signal. The interaction between the components is controlled by the state controller. The specific structure and logical relationship of each part are described below. 1: Generator           Clock generator Clkgen uses the external clock signal CLK to generate a series of clock signals CLK1, fetch, ALU_CLK to other parts of the CPU. Where fetch is the eight-way signal from the external clock clk. Use the rising edge of fetch to trigger the CPU controller to start executing an instruction, while the fetch signal will also control the address multiplexer output instruction address and data address. The CLK1 signal is used as the clock signal of the instruction register, accumulator, and state controller. The ALU_CLK is used to trigger the arithmetic logic unit. The waveform of the clock generator Clkgen is shown below: Its VERILOGHDL program is described in the following module:

Module Clk_gen (CLK,RESET,CLK1,CLK2,CLK4,FETCH,ALU_CLK); input Clk,reset;output Clk1,clk2,clk4,fetch,alu_clk;wire Clk,reset;reg clk2,clk4,fetch,alu_clk;reg[7:0] State;parameter S1 = 8 ' b00000001,s2 = 8 ' B00000010,S3 = 8 ' b00000100,S4 = 8 '  B00001000,S5 = 8 ' b00010000,s6 = 8 ' b00100000,s7 = 8 ' B01000000,s8 = 8 ' B10000000,idle = 8 ' b00000000;assign clk1 = ~clk;always @ (Negedge CLK) if (reset) beginclk2 <= 0;clk4 <= 1;fetch <= 0;alu_clk <= 0;state <= idle;endelsebegincase (STA TE) s1:beginclk2 <= ~clk2;alu_clk <= ~alu_clk;state <= s2;ends2:beginclk2 <= ~clk2;clk4 <= ~clk4;alu_clk &L  t;= ~alu_clk;state <= s3;ends3:beginclk2 <= ~clk2;state <= s4;ends4:beginclk2 <= ~clk2;clk4 <= ~clk4;fetch  <= ~fetch;state <= s5;ends5:beginclk2 <= ~clk2;state <= s6;ends6:beginclk2 <= ~clk2;clk4 <= ~clk4;state  <= s7;ends7:beginclk2 <= ~clk2;state <= s8;ends8:beginclk2 <= ~clk2;clk4 <= ~clk4;fetch <= ~fetch;state <= s1;endidle:state <= S1;deFault:state <= idle;endcaseendendmodule//-------------------------------------------------------------------- ------------

Because the design method of synchronous state machine is adopted in the design of clock generator, not only the source program of Clk_gen module can be synthesized by various kinds of synthesizer, but also the CLK1, CLK2, CLK4, Fetch and ALU_CLK generated by it are obviously improved in the time synchronization performance of jump change. It lays a good foundation for the performance improvement of the whole system.
The 2 instruction register, as its name implies, is used to register instructions.
The trigger clock of the instruction register is CLK1, and the register sends the instruction from the data bus to a high 8-bit or low 8-bit register, triggered by the positive edge of the CLK1. But not every clk1 on the rising edge of the data bus is stored, because the data bus sometimes transmission instructions, and sometimes transmission of information. When to register, when not to register the LOAD_IR signal control by the CPU State controller. The load_ir signal is entered into the instruction register via the ENA port. After reset, the instruction register is cleared to zero.
Each instruction is 2 bytes, or 16 bits. The high 3 bits are opcode, and the low 13 bits are the addresses. (The address bus for the CPU is 13 bits and the addressing space is 8K bytes.) The data bus for this design is 8 bits, so each instruction needs to be taken two times. Take the high 8 bits first, then take the lower 8 bits. The current fetch is either a high 8-bit or a low 8-bit, which is recorded by the variable state. A state of zero indicates a high 8-bit, a high 8-bit register, and a variable state of 1.        The next time the deposit, because the state is 1, it is known to take a low 8 bits, deposited in a low 8-bit register. See the following module for its VERILOGHDL program:

---------------------------------------------------------------Module Register (opc_iraddr,data,ena,clk1,rst) ; output [15:0] opc_iraddr;input [7:0] data;input ena, CLK1, Rst;reg [15:0] Opc_iraddr;reg state;always @ (Posedge clk1) Begi NIF (RST) beginopc_iraddr<=16 ' b0000_0000_0000_0000;state<=1 ' b0;endelsebeginif (ENA)//If the load instruction register signal Load_ir arrives, Begin//Divide two clocks each time 8-bit load instruction register casex (state)//First high byte, post low byte 1 ' b0:beginopc_iraddr[15:8]<=data;state<=1;end1 ' B1:beginopc _iraddr[7:0]<=data;state<=0;enddefault:beginopc_iraddr[15:0]<=16 ' bxxxxxxxxxxxxxxxx;state<=1 ' bx; Endendcaseendelsestate<=1 ' b0;endendendmodule//--------------------------------------------------------

3. Accumulator accumulator is used to store the current result, which is also one of the data sources of binocular operation. After the reset, the value of the accumulator is zero. When the accumulator receives the LOAD_ACC signal from the CPU status controller through the ENA port, it receives data from the bus when the CLK1 clock is jumping along.
See the following module for its VERILOGHDL program:

--------------------------------------------------------------Module Accum (accum, data, ENA, CLK1, rst); output[ 7:0]accum;input[7:0]data;input Ena,clk1,rst;reg[7:0]accum; [Email protected] (Posedge clk1) beginif (RST) accum<=8 ' b0000_0000; Resetelseif (ENA)//When the CPU status controller emits a LOAD_ACC signal accum<=data; Accumulateendendmodule

4 arithmetic logic operation unit according to the input of the 8 different operation code to achieve the corresponding addition, and, XOR, jump and other 8 basic operation operations. Many other operations, such as logical judgments, can be implemented using these basic operations.
See the following module for its VERILOGHDL program:

//------------------------------------------------------------------------------ Module Alu (alu_out, zero, data, accum, alu_clk, opcode); output [7:0]alu_out;output zero;input [7:0] Data, Accum;input [2: 0] Opcode;input Alu_clk;reg [7:0] alu_out;parameter HLT =3 ' b000,skz =3 ' b001,add =3 ' b010,andd =3 ' B011,XORR =3 ' B100,LDA = 3 ' B101,sto =3 ' b110,jmp =3 ' b111;assign zero =!accum;always @ (POSEDGEALU_CLK) begin//opcode output from instruction register opc_iaddr<15..0> Low 3-bit casex (opcode) hlt:alu_out<=accum; skz:alu_out<=accum; add:alu_out<=data+accum; andd:alu_out<=data&accum; xorr:alu_out<=data^accum; lda:alu_out<=data; sto:alu_out<=accum; Jmp:alu_out<=accum;default:alu_out<=8 ' bxxxx_xxxx;endcaseendendmodule//---------------------------------- ------------------------------------------

5. The function of the data controller data controller is to control the accumulator data output, because the data bus is a common channel for transmitting data in various operations, and different contents are transmitted in different situations. Sometimes it is time to transfer instructions, sometimes to transfer data from the Ram area or interface. The accumulator's data is allowed to output only when it needs to be written to the Ram area or port, otherwise high impedance States should be present to allow other components to use the data bus. So any component that outputs data to the bus requires a control signal. The start and stop of this control signal is determined by each signal control output by the CPU state controller. When the data controller outputs the data of the accumulator, it is determined by the control signal Datactl_ena output by the state controller.
See the following module for its VERILOGHDL program:

--------------------------------------------------------------------module Datactl (data,in,data_ena); output [ 7:0]data;input [7:0]in;input data_ena;assign data = (Data_ena)? In:8 ' bzzzz_zzzz;endmodule//--------------------------------------------------------------------

6. Address Multiplexer address multiplexer is used to select the address of the output is the PC (program count) address or data/port address. The first 4 clock cycles of each instruction cycle are used to read the instruction from ROM and the output should be the PC address. The latter 4 clock cycles are used to read and write to the RAM or port, which is given in the instruction.        The selected output signal of the address is provided by a 8-way signal fetch of the clock signal. See the following module for its VERILOGHDL program:

------------------------------------------------------------------------------module ADR (ADDR,FETCH,IR_ADDR, PC_ADDR); output [12:0] addr;input [12:0] ir_addr, pc_addr;input fetch;assign addr = fetch? pc_addr:ir_addr;endmodule//------------------------------------------------------------------------------

7. The Program Counter program counter is used to provide the instruction address. In order to read instructions, the instructions are stored in the memory in order of address. There are two ways to form an instruction address: one is sequential execution, and the other is the case of changing the sequence of execution procedures, such as the need to form a new command address after executing the JMP command. After reset, the instruction pointer is zero, that is, each time the CPU restarts, the instruction is read from the 0 address of the ROM and executed. After each instruction executes 2 clocks, the PC_ADDR has been increased by 2, pointing to the next instruction. (because each instruction occupies two bytes.) If the instruction being executed is a jump statement, then the CPU state controller will output the LOAD_PC signal and enter the program counter through the load port. The program counter (PC_ADDR) will be loaded into the destination address (IR_ADDR) instead of increasing by 2.
See the following module for its VERILOGHDL program:

------------------------------------------------------------------------------Module Counter (pc_addr, IR_ADDR, Load, clock, rst); output [12:0] pc_addr;input [12:0] ir_addr;input load, clock, Rst;reg [12:0] pc_addr;always @ (Posedge C Lock or Posedge rst) beginif (RST) pc_addr<=13 ' B0_0000_0000_0000;elseif (load) pc_addr<=ir_addr;elsepc_addr <= Pc_addr + 1;endendmodule//------------------------------------------------------------------------------

8. The state Controller State controller consists of two parts:

1. State machines (machine part in)
2. State controller (machinectl section in)

The state machine controller accepts the reset signal rst, and when the RST is valid, it is ENA by the signal to 0, and the input to the state machine stops the state machine from working.
The VERILOGHDL program for the state controller is shown in the following module:

------------------------------------------------------------------------------Module Machinectl (ENA, Fetch, RST ); output ena;input fetch, Rst;reg ena;always @ (Posedge fetch or Posedge rst) beginif (RST) ena<=0;elseena<=1; endendmodule//------------------------------------------------------------------------------

The state machine is the CPU's control core, which is used to generate a series of control signals to start or stop certain parts. When the CPU reads and writes the I/O port, the Ram area is controlled by the state machine. The current state of the state machine, which is recorded by the variable states, which is the number of clocks that have been in the current instruction cycle (from 0). The instruction cycle is made up of 8 clock cycles, each of which has to complete a fixed operation.

1. The No. 0 clock, because the output of the CPU state Controller: RD and Load_ir are high, and the rest are low. The instruction register registers a high 8-bit instruction code sent by the ROM.
2. The 1th clock, compared to 1: only inc_pc from 0 to 1 so the PC 1,rom sent low 8-bit instruction code, instruction register to register the 8-bit code.
3. 2nd clock, empty operation.
4. 3rd clock, PC 1, point to next instruction. If the operator is HLT, the output signal hlt is high. If the operator is not hlt, the output of the other control lines is zero except for the addition of the PC (referring to the next instruction).
5. The 4th clock, if the operator is and, ADD, XOR or LDA, reads the data of the corresponding address; If you are in jmp, send the destination address to the program counter, and if it is sto, output the accumulator data.
6. The 5th clock, if the operator is andd, add or Xorr, the arithmetic operator to do the corresponding operation, if LDA, the data through the arithmetic operator to the accumulator, if the SKZ, first determine whether the value of the accumulator is 0, if the 0,pc increase 1, otherwise maintain the original value; The lock destination address, or, if STO, writes the data to the address.
7. 6th clock, empty operation.
8. 7th Clock, if the operator is SKZ and the accumulator value is 0, then the PC value is increased by 1, skipping an instruction, otherwise the PC has no change.

The VERILOGHDL program of the state machine is shown in the following module:

------------------------------------------------------------------------------module Machine (INC_PC, LOAD_ACC, LOAD_PC, RD,WR, Load_ir,datactl_ena, Halt, Clk1, zero, ena, opcode); output inc_pc, LOAD_ACC, load_pc, RD, WR, Load_ir;out Put Datactl_ena, Halt;input Clk1, Zero, ena;input [2:0] Opcode;reg inc_pc, LOAD_ACC, load_pc, RD, WR, Load_ir;reg Datactl_ Ena, Halt;reg [2:0] state;parameter HLT = 3 ' B000,skz = 3 ' B001,add = 3 ' b010,andd = 3 ' B011,xorr = 3 ' B100,lda = 3 ' b101, STO = 3 ' b110,jmp = 3 ' b111;always @ (Negedge clk1) beginif (!ena)//received reset signal RST, reset operation Beginstate<=3 ' b000; {inc_pc,load_acc,load_pc,rd}<=4 ' b0000; {wr,load_ir,datactl_ena,halt}<=4 ' b0000;endelsectl_cycle;end//-----------------begin of Task Ctl_ Cycle---------Task Ctl_cycle;begincasex (State) 3 ' b000://load, 8bits in Structionbegin{inc_pc,load_acc,load_pc,rd }<=4 ' b0001; {wr,load_ir,datactl_ena,halt}<=4 ' b0100;state<=3 ' B001;end3 ' b001://PC increased by one then load low 8bits Instructionbegin{inc_pc,load_acc,load_pc,rd}<=4 ' b1001; {wr,load_ir,datactl_ena,halt}<=4 ' b0100;state<=3 ' B010;end3 ' b010://idlebegin{inc_pc,load_acc,load_pc,rd} <=4 ' b0000; {wr,load_ir,datactl_ena,halt}<=4 ' b0000;state<=3 ' B011;end3 ' b011://next instruction Address Setup The analysis instruction starts here beginif (OPCODE==HLT)//Instruction for pause hltbegin{inc_pc,load_acc,load_pc,rd}<=4 ' b1000; {wr,load_ir,datactl_ena,halt}<=4 ' b0001;endelsebegin{inc_pc,load_acc,load_pc,rd}<=4 ' b1000; {wr,load_ir,datactl_ena,halt}<=4 ' b0000;endstate<=3 ' B100;end3 ' b100://fetch oprandbeginif (Opcode==JMP) begin {inc_pc,load_acc,load_pc,rd}<=4 ' b0010; {wr,load_ir,datactl_ena,halt}<=4 ' B0000;endelseif (opcode==add | | opcode==andd | | Opcode==xorr | | Opcode==lda) begin{inc_pc,load_acc,load_pc,rd}<=4 ' b0001; {wr,load_ir,datactl_ena,halt}<=4 ' B0000;endelseif (opcode==sto) begin{inc_pc,load_acc,load_pc,rd}<=4 ' b0000; {wr,load_ir,datactl_ena,halt}<=4 ' b0010;endelsebegin{inc_pc,load_acc,load_pc,rd}<=4 ' b0000; {wr,load_ir,datactl_ena,halt}<=4 ' b0000;endstate<=3 ' B101;end3 ' b101://operationbeginif (opcode==add| | opcode==andd| | opcode==xorr| | Opcode==lda) begin//After a clock and operate with the contents of the accumulator {inc_pc,load_acc,load_pc,rd}<=4 ' b0101; {wr,load_ir,datactl_ena,halt}<=4 ' B0000;endelseif (opcode==skz && zero==1) begin{inc_pc,load_acc,load_pc , rd}<=4 ' b1000; {wr,load_ir,datactl_ena,halt}<=4 ' B0000;endelseif (opcode==jmp) begin{inc_pc,load_acc,load_pc,rd}<=4 ' b1010; {wr,load_ir,datactl_ena,halt}<=4 ' B0000;endelseif (opcode==sto) begin//a clock after the change of WR to 1 can be written into RAM {INC_PC,LOAD_ACC, Load_pc,rd}<=4 ' b0000; {wr,load_ir,datactl_ena,halt}<=4 ' b1010;endelsebegin{inc_pc,load_acc,load_pc,rd}<=4 ' b0000; {wr,load_ir,datactl_ena,halt}<=4 ' b0000;endstate<=3 ' B110;end3 ' b110://idlebeginif (Opcode==STO) begin{inc_pc , load_acc,load_pc,rd}<=4 ' b0000; {wr,load_ir,datactl_ena,halt}<=4 ' B0010;endelseif (opcode==add| | opcode==andd| | opcode==xorr| | Opcode==lda) begin{inc_pc,load_acc,load_pc,rd}<=4 ' b0001; {wr,load_ir,datactl_ena,halt}<=4 ' B0000;endelsebegin{inc_pc,load_acC,load_pc,rd}<=4 ' b0000; {wr,load_ir,datactl_ena,halt}<=4 ' b0000;endstate<=3 ' B111;end3 ' b111://beginif (opcode==skz && zero==1 ) begin{inc_pc,load_acc,load_pc,rd}<=4 ' b1000; {wr,load_ir,datactl_ena,halt}<=4 ' b0000;endelsebegin{inc_pc,load_acc,load_pc,rd}<=4 ' b0000; {wr,load_ir,datactl_ena,halt}<=4 ' b0000;endstate<=3 ' b000;enddefault:begin{inc_pc,load_acc,load_pc,rd}< =4 ' b0000; {wr,load_ir,datactl_ena,halt}<=4 ' b0000;state<=3 ' b000;endendcaseendendtask//-----------------end of Task ctl _cycle---------endmodule//------------------------------------------------------------------------------

9. Peripheral module in order to test the RISC_CPU, it is necessary to have the ROM of the stored test program and the RAM and address decoder to load the data. Here's a quick introduction:
Address decoder

Module Addr_decode (addr, Rom_sel, Ram_sel); output Rom_sel, Ram_sel;input [12:0] Addr;reg Rom_sel, ram_sel;always @ (addr ) begincasex (addr) ' b1_1xxx_xxxx_xxxx:{rom_sel,ram_sel}<=2 ' b01;13 ' b0_xxxx_xxxx_xxxx:{rom_sel,ram_sel}<=2 ' b10;13 ' b1_0xxx_xxxx_xxxx:{rom_sel,ram_sel}<=2 ' b10;default:{rom_sel,ram_sel}<=2 ' b00;endcaseendendmodule

The address decoder is used to generate a pass-through signal, select the ROM or RAM.
FFFFH---1800H RAM
1800H---0000H romram

Module RAM (data, addr, Ena, read, write); inout [7:0] data;input [9:0] addr;input ena;input Read, Write;reg [7:0] RAM [10 ' H3ff:0];assign data = (read && ena)? RAM[ADDR]: 8 ' hzz;always @ (Posedge write) Beginram[addr]<=data;endendmodule

Rom

Module ROM (data, addr, read, ENA), output [7:0] data;input [12:0] addr;input read, Ena;reg [7:0] memory [H1fff:0];wire] [7:0] data;assign data= (read && ena)? MEMORY[ADDR]: 8 ' bzzzzzzzz;endmodule

ROM is used to load the test program, readable and non-writable. RAM is used to hold data, readable and writable.

Third, RISC CPU components of the mutual connection relationship four, RISC CPU and its peripheral circuit five, RISC CPU addressing mode and instruction system RISC_CPU instruction format is: Instruction system consists of only 8 instructions:

• 1) HLT stop operation. This operation will empty an instruction cycle, that is, 8 clock cycles.
• 2) SKZ 0 skips the next statement. This operation first to determine whether the results of the current Alu is zero, if 0 skips the next statement, otherwise continue execution.
• 3) Add adds. This action adds the value in the accumulator to the memory or port that the address refers to, and the result is returned to the accumulator.
• 4) and phases. This operation will return the value of the accumulator to the data of the memory or port to which the address refers, and the result is still returned to the accumulator.
• 5) XOR different or. This operation will add the value of the accumulator to the address given in the instruction and the result will still be returned to the accumulator.
• 6) LDA read data. This action puts the data for the address in the instruction into the accumulator.
• 7) STO writes data. This operation puts the data of the accumulator into the address given in the instruction.
• 8) JMP unconditional jump statement. The operation will jump to the destination address given by the instruction and continue execution.

The RISC_CPU is a 8-bit microprocessor that uses direct addressing, where the data is always placed in memory, and the address of the addressing unit is given directly by the instruction. This is the simplest way to address. Vi. operation and timing of RISC CPUs a microcomputer system needs to perform many operations on the CPU in order to accomplish its functions. The following are the main operations of RISC_CPU:

• 1. System reset and start-up operation
• 2. Bus read operation
• 3. Bus write operation

Here is a detailed description of each operation: 1. The reset and start-up operation of the RISC_CPU system is triggered by a signal from the RST pin. When the RST signal enters high, the RISC_CPU will end the current operation and the CPU will remain in the reset state as long as the RST is stuck in a high level state. In the reset state, each internal register of the CPU is set to the initial value, all zeros. The data bus is high impedance state, address bus is 0000H, all control signals are invalid. After the RST returns to the low level, then the first fetch rising edge will start risc_cpu to start working, reading the instruction from 000 of the ROM and performing the appropriate action. The waveform diagram is shown. The dotted line flag is at the moment when the RISC_CPU starts working. RISC_CPU Reset and start-up Operation Waveform 2. Bus read operations The first 0--3 clock cycles of each instruction cycle are used for read instructions, which are described in detail in the State Controller section and are not repeated here. During the 3.5 cycle, the memory or port address is output to the address bus, the 4--6 clock cycle, the read Signal Rd valid, the data is sent to the bus, in case the accumulator is latched, or participate in arithmetic, logic operation. 7th clock cycle, read signal invalid, 7.5 period, address bus output PC address, ready for the next command. The timing of the CPU reading data from memory or Port 3 write bus operation at the 3.5 clock cycle of each instruction cycle, the written address is established, the 4th clock cycle output data, and the 5th clock cycle output write signal. To the end of the 6th clock, the data is invalid, the 7.5 clock address output is the PC address, ready for the next instruction cycle. Original address: http://blog.csdn.net/ce123_zhouwei/article/details/7180066

A simple RISC CPU design based on state machine