A simple simulation process based on Modelsim-se-

Simple simulation process based on Modelsim-se-the next compilation

in the WorkSpace window counter_tst.v Right click, if you choose Compile selected Compile the selected file, Compile All is to compile all files, here Select Compile-> Compile all, as shown;

The green font appears in the Script window:

# Compile of COUNTER.V was successful.

# Compile of COUNTER_TST.V was successful., stating that the file was compiled successfully, there is a green checkmark after the status bar of the file, indicating that the compilation was successful, and that if there is a red font, there is a syntax error in the RTL file. At this point, you can double-click the red font will pop up the window, display the specific syntax error message, the error message will indicate the syntax of the specific error reason and the location of the error, here you can double-click the error description, the software will automatically jump to the corresponding RTL file in the wrong location, then you can find in the wrong location syntax error Recompile after modification.

At the same time, the Status column appears with two question marks turned to √, indicating a successful compilation with no syntax errors.

Adding simulation signals

Let's start the simulation and click on the menu Simulate->start Simulation.

appear as shown in the interface, expand the work Library under the Design tab, and select the COUNTER_TST, which is the work in simulate. Counter_tst that the object to be simulated, in the optimization of the column does not choose optimization, if the selection of optimization, some signals will be optimized when the simulation, can not be observed. Click OK;

Click OK, the selected simulation module will be loaded into the project for simulation, there may be errors, the general problem is in the testbench of the module name, the module signal error or signal parameters have errors, if there is an error, you need to modify and then recompile the module to be tested to load the project.

After the load is successful, the project work window jumps to the SIM window and the following interface appears:

In the SIM window you can see the 3 parts of the Testbench design, initialized, always, and instantiated modules. The signal to be observed here is to instantiate the signal of the module output, right-click on the counter_1, select Add->add to wave, add the signal of the module to be tested to the Waveform Observation window for simulation observation.

After adding the Wave window as shown in

Simulation begins

The simulation can be set using the toolbar on the window, as shown in

You can also run by pressing ENTER after entering run time in the Script window: Run 1ms, which runs 1ms.

Simulation Signal Viewing

After the simulation runs, the waveform window will appear as shown below.

Here the signal counter_out is selected, right-click as shown, set the signal display of the numbering, here Select the unsigned shaping to display.

You can see that the signal is added by 0 on each rising edge of the clock, and again after counting to 255 and counting again from 0.

In the signal display, sometimes in order to observe the signal more directly, the signal needs to be simulated to display, Modelsim software can meet this requirement, here Select Counter_out Signal, right click as shown

Set the signal to analog display, then pop up the following window, you can set the adjustment signal display amplitude, here Default original value, click OK.

Finally, set the width of the analog signal display in the waveform window to meet the signal after the analog display will not overlap with other signal display. Select the Counter_out signal and right-click as shown.

To set the signal display format, as shown here, set the display height is 300, can meet the signal maximum value of 255.

Finally, it can be seen that displaying the counter_out as an analog signal results in the following.

A simple simulation process based on Modelsim-se-