V = 0 ~ 0x00000000 ~ 0x0000001CV = 1 ~ 0xffff0000 ~ 0xffff001C // cost 2.1 cr_alignment // gliethttp arch/arm/kernel/entry-armv.SENTRY (stext) mov r12, r0 mov r0, # F_BIT | I _BIT | MODE_SVC @ make sure svc mode msr cpsr_c, r0 @ and all irqs disabled // _ lookup_processor_type query the processor type, [gliethttp
Make up later
<浅析head-armv.s>
] Return Value // 2007-07-04 // r9 = processor ID // read the c0 register of cp15 // r10 = pointer to processor structure
// The following will add pc, r10, #12, jump to _ arm920_setup // gliethttp in the vmlinux-armv.lds.in // _ proc_info_begin = .; // * (.proc.info) // _ proc_info_end = .; // see 2.2 bl _ lookup_processor_type teq r10, #0 @ invalid processor? Moveq r0, # 'P' @ yes, error 'P' beq _ error bl _ lookup_ubunture_type teq r7, #0 @ invalid architecture? Moveq r0, # 'A' @ yes, error 'A' beq _ error // _ create_page_tables create the first 4 MB page table bl _ create_page_tables for temporary arm startup. lr, _ ret @ return address add pc, r10, #12 @ initialise processor. type _ switch_data, % object _ switch_data :. long _ mmap_switched. long SYMBOL_NAME (_ bss_start ). long SYMBOL_NAME (_ end ). long SYMBOL_NAME (processor_id ). long SYMBOL_NAME (_ machine_arch_type ). long SYMBOL_NAME (cr_alignment ). Long SYMBOL_NAME (init_task_union) + 8192/** Enable the MMU. this completely changes the structure of the visible * memory space. you will not be able to trace execution through this. * If you have an enquiry about this, * please * check the linux-arm-kernel * mailing list archives BEFORE sending another post to the list. */. type _ ret, % function _ ret: ldr lr, _ switch_data mcr p15, 0, r0, c1, c0/ /Place the r0 value set in _ arm920_setup into the mrc p15, 0, r0, c1, c0, 0 @ read it back in the cp15 coprocessor c1 register. mov r0, r0 // fill in the Three-Level assembly line in armv4: mov r0, r0 corresponds to a nop, so it corresponds to two nop and one mov pc, lr is just three "useless" operations mov r0, r0 mov pc, lr // jump to The _ mmap_switched function gliethtttp/** the following fragment of code is executed with The MMU on, and uses * absolute addresses; this is not position independent. ** r0 = processor control register * r1 = machine ID * R9 = processor ID */. align 5 _ mmap_switched: adr r3, _ switch_data + 4 ldmia r3, {r4, r5, r6, r7, r8, sp} @ r2 = compat // 2007-07-04 gliethttp // r4 ~ _ Bss_start // r5 ~ _ End // r6 ~ Processor_id // r7 ~ _ Machine_arch_type // r8 ~ Cr_alignment // sp ~ (Init_task_union) + 8192 // perform the following operations on processor_id ,__ machine_arch_type, cr_alignment assigned gliethttp mov fp, #0 @ Clear BSS (and zero fp) 1: cmp r4, r5 // clear 0 strcc fp, [r4], #4 bcc 1b str r9, [r6] @ Save processor ID str r1, [r7] @ Save machine type # ifdef CONFIG_ALIGNMENT_TRAP orr r0, r0, #2 @........... a. # endif bic r2, r0, #2 @ clear'a' bit // r2 stores the r0 value after the TRAP queue is disabled. // r8-> cr_alignment, cr_no_alignment // After stmia r8, {r0, r2}, cr_alignment = r0, cr_no_alignment = r2 stmia r8, {r0, r2} @ Save control register values B SYMBOL_NAME (start_kernel) // enter the kernel C program // -------------------------------------- 2.2 _ arm920_proc_info/gliethttp arch/arm/mm/proc-arm920.S.section ".proc.info", # alloc, # execinstr. type _ arm920_proc_info, # object _ arm920_proc_info: // This address is stored in r10. long 0x41009200. long 0xff00fff0. long 0x00000c1e @ mmuflags B _ arm920_setup // add pc, r10, #12 gliethttp will make the cpu execute the B _ arm920_setup jump command. long cpu_arch_name. long cpu_elf_name. long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB. long cpu_arm920_info. long arm920_processor_functions. size _ arm920_proc_info ,. -_ arm920_proc_info // ------------------------------------------ 2.3 _ arm920_setup. section ". text. init ", # alloc, # execinstr _ arm920_setup: mov r0, #0 mcr p15, 0, r0, c7, c7 @ invalidate I, D caches on v4 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 mcr p15, 0, r0, c8, c7 @ invalidate I, D TLBs on v4 mcr p15, 0, r4, c2, c0 @ load page table pointer mov r0, # 0x1f @ Domains 0, 1 = client mcr p15, 0, r0, c3, c0 @ load domain access register mrc p15, 0, r0, c1, c0 @ get control register v4/** Clear out 'unwanted' bits (then put them in if we need them) * // The gliethttp r0 unit stores the value of the c1 register of the cp15 coprocessor. The following code processes the value @ VI zfr bldp wcam bic r0, r0, #0x0e00 // clear 0 bit [9 .. 11] bic r0, r0, #0x0002 // clear 0 bit [1] bic r0, r0, # 0x000c bic r0, r0, #0x1000 @... 0 000 ..... 000. /** Turn on what we want */orr r0, r0, #0x0031 // bit0 = 1 enable mmu orr r0, r0, #0x2100 @.. 1 .... 1 .. 11... 1
// Bit13 = 1 the base address of the interrupt vector table is 0xFFFF0000 # ifndef CONFIG_CPU_DCACHE_DISABLE orr r0, r0, #0x0004 @............. 1 .. # endif # ifndef CONFIG_CPU_ICACHE_DISABLE orr r0, r0, #0x1000 @... 1 ............ # endif mov pc, lr
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